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 PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
1/3-INCH SOC MEGAPIXEL CMOS DIGITAL IMAGE SENSOR
Features
* DigitalClarity CMOS Imaging Technology * System-on-a-Chip (SOC)--Completely integrated camera system * Ultra-low power, low cost, progressive scan CMOS image sensor * Superior low-light performance * On-chip image flow processor (IFP) performs sophisticated processing: Color recovery and correction Sharpening, gamma, lens-shading correction On-the-fly defect correction * Filtered image downscaling to arbitrary size with smooth, continuous zoom and pan * Automatic Features: Auto exposure, auto white balance (AWB), auto black reference (ABR), auto flicker avoidance, auto color saturation, auto defect identification and correction * Fully automatic Xenon and LED-type flash support Fast exposure adaptation * Multiple parameter contexts Easy/fast mode switching * Camera control sequencer automates: Snapshots Snapshots with flash Video clips * Simple two-wire serial programming interface * ITU-R BT.656 (YCbCr), 565RGB, 555RGB, or 444RGB formats (progressive scan) * Raw and processed Bayer formats * Output FIFO and integer clock divider: "Uniform" pixel clocking
MT9M111I29STC
(Micron Part Number)
Table 1:
PARAMETER
Key Performance Parameters
TYPICAL VALUE 1/3-inch (5:4) 4.6mm(H) x 3.7mm (V), 5.9mm diagonal 1,280H x 1,024V 3.6m x 3.6m RGB Bayer Pattern Electronic Rolling Shutter (ERS) 27 MPS/54 MHz 15 fps at 54 MHz 30 fps at 54 MHz 10 bit, dual on-chip 1.0 V/lux-sec (550nm) 71dB 44dB 1.7V-3.6V 2.5V-3.1V 2.5V-3.1V 170mW SXGA at 15 fps (54 MHz CLKIN) 90mW QSXGA at 30 fps (54 MHz low-power mode) -30C to +70C 44-Ball iCSP wafer or die
Optical Format Active Imager Size Active Pixels Pixel Size Color Filter Array Shutter Type Maximum Data Rate/ Maximum Master Clock Frame SXGA Rate (1,280 x 1,024) QSXGA (640 x 512) ADC Resolution Responsivity Dynamic Range SNRMAX I/O Digital Core Digital Analog Power Consumption Supply Voltage
Operating Temperature Packaging
Applications
* * * * Cellular phones PDAs Toys Other battery-powered products
09005aef8136743e pdf/09005aef8136761e zip MT9M111__SOC1310__1.fm - Rev. C 10/04 EN
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(c)2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Register Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Sensor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Lens-Shading Correction and Black Level Conditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Defect Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Interpolation, Aperture, and Color Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Resize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Camera Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Camera Interface and Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contexts, Snapshots, and Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Output Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 IFP Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 IFP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Sensor Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Sensor Core Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Sensor Core Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Sensor Read Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Contexts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Viewfinder/Preview and Full-Resolution/Snapshot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Low-Power Preview Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Full-Resolution Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Switching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Primary Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Full-Power Readout Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Low-Power Readout Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Tuning Frame Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Default Blanking Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 [REG | REG]: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 User Blanking Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Exposure and Sensor Context Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Switching From Context A to B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Horizontal Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Switching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Simple Snapshots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Typical Resolutions, Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Reset, Clocks, and Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
09005aef8136743e pdf/09005aef8136761e zip MT9M111__SOC1310TOC.fm - Rev. C 10/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 APPENDIX A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Two-Wire Serial Interface Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Write and Read Sequences (SADDR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 16-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 8-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 8-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Two-Wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Data Sheet Designation: Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
09005aef8136743e pdf/09005aef8136761e zip MT9M111__SOC1310TOC.fm - Rev. C 10/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Internal Registers Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Typical Configuration (Connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 44-Ball iCSP Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Spatial Illustration of Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Primary Sensor Core Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Horizontal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 I/O Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Spectral Response Chart (Preliminary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Optical Center Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Write Timing to R0x09:0--Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Read Timing from R0x09:0; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Write Timing to R0x09:0--Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Read Timing from R0x09:0; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Serial Host Interface: Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Serial Host Interface: Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Serial Host Interface Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Serial Host Interface Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Acknowledge Signal Timing After an 8-Bit Write to Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Acknowledge Signal Timing After an 8-Bit Read from Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 44-Ball iCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Data Ordering in YCbCr Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Output Data Ordering in Processed Bayer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Output Data Ordering in RGB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Output Data Ordering in (8 + 2) Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Colorpipe Registers (Address Page 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Camera Control Registers (Address Page 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Colorpipe Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Camera Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Sensor Registers (Address Page 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Sensor Core Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Register Address Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Blanking Parameter Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 User Blanking Minimum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Blanking Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 I/O Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Power Consumption at 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 I/O Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
General Description
The Micron(R) Imaging MT9M111 is an SXGA-format single-chip camera with a 1/3-inch CMOS active-pixel digital image sensor. This device combines the MT9M011 image sensor core with fourth-generation digital image flow processor technology from Micron Imaging. It captures high-quality color images at SXGA resolution. The MT9M111 features DigitalClarity, Micron's breakthrough, low-noise CMOS imaging technology that achieves CCD image quality (based on signal-tonoise ratio and low-light sensitivity) while maintaining the inherent size, cost and integration advantages of CMOS. The sensor is a complete camera-on-a-chip solution designed specifically to meet the low-power, lowcost demands of battery-powered products such as cellular phones, PDAs, and toys. It incorporates sophisticated camera functions on-chip and is programmable through a simple two-wire serial interface. The MT9M111 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50Hz/60Hz flicker avoidance, lens-shading correction, auto white balance (AWB), and on-the-fly defect identification and correction. Additional features include day/night mode configurations; special camera effects such as sepia tone and solarization; and interpolation to arbitrary image size with continuous filtered zoom and pan. The device supports both Xenon and LEDtype flash light sources in several snapshot modes. The MT9M111 can be programmed to output progressive-scan images up to 30 frames per second (fps) in preview power-saving mode, and 15 fps in full-resolution (SXGA) mode. In either mode, the image data can be output in any one of six 8-bit formats: * ITU-R BT.656 (formerly CCIR656, progressive scan only) YCbCr * 565RGB * 555RGB * 444RGB * Raw Bayer * "Processed" Bayer The FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Functional Overview
The MT9M111 is a fully-automatic, single-chip camera, requiring only a power supply, lens and clock source for basic operation. Output video is streamed via a parallel 8-bit DOUT port, shown in Figure 1 on page 8. The output pixel clock is used to latch data, while FRAME_VALID and LINE_VALID signals indicate the active video. The MT9M111 internal registers are configured using a two-wire serial interface. The device can be put in low-power sleep mode by asserting the standby pin and shutting down the clock. Output pins can be tri-stated by de-asserting the OE# pin. Both tri-stating output pins and entry in standby mode also can be achieved via two-wire serial interface register writes. The MT9M111 accepts input clocks up to 54 MHz, delivering up to 15 fps for SXGA resolution images, and up to 30 fps for QSXGA (full field-of-view, sensor pixel skipping) images. The device also supports a lowpower preview configuration that delivers SXGA images at 7.5 fps and QSXGA images at 30 fps. The device can be programmed to slow the frame rate in low-light conditions to achieve longer exposures and better image quality. Internal Architecture Internally, the MT9M111 consists of a sensor core and an IFP. The IFP is divided in two sections: the colorpipe (CP), and the camera controller (CC). The sensor core captures raw Bayer-encoded images that are then input in the IFP. The CP section of the IFP processes the incoming stream to create interpolated, color-corrected output, and the CC section controls the sensor core to maintain the desired exposure and color balance, and to support snapshot modes. The sensor core, CP and CC registers are grouped in three , separate address spaces, shown in Figure 2. When accessing internal registers via the two-wire serial interface, select the desired address space by programming the R240 shared register. The MT9M111 accelerates mode switching with hardware-assisted context switching, and supports taking snapshots, flash snapshots, and video clips using a configurable sequencer. The MT9M111 supports a range of color formats derived from four primary color representations: YCbCr, RGB, raw Bayer (unprocessed, directly from the sensor), and processed Bayer (Bayer format data regenerated from processed RGB). The device also supports a variety of output signaling/timing options: * Standard FRAME_VALID/LINE_VALID video interface with gated pixel clocks * Standard video interface with uniform clocking * ITU-R BT.656 marker-embedded video interface with either gated or uniform pixel clocking. Register Notation The following register address notations are used in this document: * R:
Example: R9:0--Shutter width register in sensor page (page 0). Used to uniquely specify a register. * R Example: R240--Page address register. Used when the register address is the same in all three pages or when by context the address page is understood. * 0x<2 digit hex address> Example: 0xF0--Page address register. Used when the register address is the same in all three pages, or when by context the address page is understood.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 1: Functional Block Diagram
SCLK SDATA
Sensor Core
1316H x 1048V including black 1/3-inch optical format Auto black compensation Programmable analog gain Programmable exposure Dual 10-bit ADCs Low-power preview mode H/W context switch to/from preview Bayer RGB output
Pixel Data
SRAM Line Buffers
CLKIN STANDBY OE#
Control Bus (Two-Wire Serial I/F Transactions)
Control Bus (Two-Wire Serial I/F Transactions) + Sensor control (gains, shutter, etc.)
Image Flow Processor Camera Control
VDDQ/DGNDQ VDD/DGND VAA/AGND VAAPIX
Control Bus (Two-Wire Serial I/F Trans.)
Image Flow Processor Colorpipe
Lens shading correction Color interpolation Filtered resize and zoom Defect correction Color correction Gamma correction Color conversion + formatting Output FIFO
DOUT[7:0]
Auto exposure Auto white balance Flicker detect/avoid Camera control: snapshots, flash, video, clip)
PIXCLK FRAME_VALID LINE_VALID STROBE
Image Data
Figure 2: Internal Registers Grouping
Image Flow Processor
Sensor Core Registers R[255:0]
Color Pipeline Registers R[255:0]
Camera Control Registers R[255:0]
R240 = 0
R240 = 1
R240 = 2
NOTE:
Internal registers are grouped in three address spaces. Program R240 to select the desired address space.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Typical Connections
Figure 3 shows typical MT9M111 device connections. For low-noise operation, the MT9M111 requires separate power supplies for analog and digital. Incoming digital and analog ground conductors can be tied together next to the die. Both power supply rails should be decoupled to ground using ceramic capacitors. The use of inductance filters is not recommended. The MT9M111 also supports different digital core (VDD/DGND) and I/O power (VDDQ/DGNDQ) power domains that can be at different voltages.
Figure 3: Typical Configuration (Connection)
1.7V-3.6V I/O Digital 2.8V Core Digital 2.8V Analog
VDD
VAAPIX
VDDQ
VDD
VAA
0.1F
1F
SADDR Two-Wire Serial Interface
Master Clock Power-on Reset
DOUT[7:0] FRAME_VALID LINE_VALID PIXCLK To CMOS Camera Port SCLK
SCLK SDATA CLKIN RESET# OE# STANDBY
1.5K DGND 1.5K VDDQ VAA/VAAPIX
STROBE
To Xenon or LED Flash Driver
SDATA 1K RESET#
0.1F + 10F 1F 0.1F 1F
DGNDQ
DGND
AGND
Digital GND
Analog GND
DGNDQ
AGND
NOTE:
1. 1.5K resistor value recommended, but may be greater for slower two-wire speed. 2. VDD, VAA, VAAPIX must all be at the same potential, though if connected, care must be taken to avoid excessive noise injection in the VAA/VAAPIX power domains.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 4: 44-Ball iCSP Assignment
1 2 3 4 5 6 7
A B C D E F G
DGND
DOUT3
DOUT2
VDDQ
CLK_IN
SCLK
DGND
DOUT4
VDD
DOUT1
DOUT0
PIXCLK
VDD
DGNDQ
DOUT5
DOUT6
DGNDQ
DGNDQ
VDDQ
SDATA1
DOUT7
VDDQ
VDDQ
DGND
DOUT LSB0 SADDR
DOUT LSB1 VDD
DGNDQ
DGNDQ
NC
VAAPIX
FRAME VALID
STAND BY
OE#
VAA
NC
DGND
LINE VALID
RESET#
VDDQ
STROBE
NC
AGND
Top View (Ball Down)
NOTE:
1. Bidirectional.
Table 2:
PIN NAME CLKIN OE# RESET# SADDR SCLK STANDBY SDATA DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT_LSB0
Pin Descriptions
PIN TYPE Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional DEFAULT OPERATION Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output DESCRIPTION Master Clock in Sensor. Active LOW: output enable for Data[7:0]. Active LOW: asynchronous reset. Two-Wire Serial Interface DeviceID selection 1:0xBA, 0:0x90. Two-Wire Serial Interface Clock. Active HIGH: disables imager. Two-Wire Serial Interface Data I/O. Pixel Data Output 0 (LSB). Pixel Data Output 1. Pixel Data Output 2. Pixel Data Output 3. Pixel Data Output 4. Pixel Data Output 5. Pixel Data Output 6. Pixel Data Output 7 (MSB). Sensor bypass mode output 0--typically left unconnected for normal SOC operation.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 2:
PIN NAME DOUT_LSB1 FRAME_VALID LINE_VALID PIXCLK STROBE AGND DGND DGNDQ VAA VAAPIX VDD VDDQ NC
NOTE:
Pin Descriptions (continued)
PIN TYPE Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Supply Supply Supply Supply Supply Supply Supply -- DEFAULT OPERATION Output Output Output Output Output DESCRIPTION Sensor bypass mode output 1--typically left unconnected for normal SOC operation. Active HIGH: FRAME_VALID; indicates active frame. Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel. Pixel Clock Output. Active HIGH: strobe (Xenon) or turn on (LED) flash. Analog Ground. Core Digital Ground. I/O Digital Ground. Analog Power (2.5V-3.1V). Pixel Array Analog Power Supply (2.5V-3.1V). Core Digital Power (2.5V-3.1V). I/O Digital Power (1.7V-3.6V). No connect.
All inputs and outputs are implemented with bidirectional buffers. Care must be taken that all inputs are driven and all outputs are driven if tri-stated.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Architecture Overview
The MT9M111 consists of a sensor core, the colorprocessing pipeline, and a measurement and controllogic block (the camera controller). The following is a brief overview of the architecture. adjustments can be made both by the user and the auto exposure unit (for dynamic saturation reduction in high or low-lighting situations).
Resize Sensor Core
The sensor core is taken from the MT9M011 standalone sensor and includes a number of features specifically targeting the mobile market. Of primary interest is support for low-power preview/viewfinding with hardware-accelerated switching to full-resolution for snapshots. This switch can be achieved without adversely affecting exposure or color balance. This enables taking single-frame and Xenon flash snapshots while minimizing snapshot lag. LED snapshots are discussed below; they also benefit significantly from this feature. The IFP can resize to virtually any output resolution through digitally filtered sub-sampling. Output resolutions include, but are not limited to, VGA, QVGA, CIF, and QCIF. When the output resolution is smaller than the sensor-generated image, smooth, continuous zoom and pan become available. The user simply defines the zoom window, pan offset, and output resolution, and the resizer calculates all other parameters for the resize function.
Camera Control
The camera controller continuously accumulates image brightness and color statistics. Two units use these measurements to adjust the sensor and colorpipe settings. The auto exposure unit adjusts gain and shutter width to maintain a user-defined luma target. The image measurement region can be modified to permit, for example, backlight compensation. The user can also control the speed and sensitivity of the algorithm from highly responsive (for LED flash and viewfinding) to somewhat dampened (for video). Finally, the unit can detect 50Hz or 60Hz rolling flicker bars (due to ambient illumination) and adjusts exposure appropriately to eliminate this adverse effect on image quality. The AWB module adjusts gains and the CCM to compensate for the effects of changing scene illumination on the quality of the color rendition. The user has control over the region of the scene to be analyzed as well as the responsivity of the algorithm to illuminant changes.
Lens-Shading Correction and Black Level Conditioning
The stream of raw data from the sensor enters the pipeline and undergoes several transformations. Image stream processing starts with conditioning the black level and applying a digital gain. The lens-shading block compensates for spatially varying signal loss caused by the lens. The block is programmable and implements separate correction functions for R,G, and B independently.
Defect Correction
Following lens correction, the data stream is analyzed for the presence of defects. A two-dimensional digital filter calculates suitable replacement values. Edge sensitivity minimizes false detections, helping to preserve image sharpness.
Interpolation, Aperture, and Color Correction
The Bayer pixel pattern data is interpolated to recover missing color components for each pixel following defect correction. Configurable aperture correction sharpens the image and to avoid amplifying noise, can be programmed to be less aggressive in lowlight conditions. The resulting interpolated RGB data passes through the current color correction matrix (CCM), gamma, and color saturation corrections. The CCM can be manually loaded or dynamically configured by the AWB unit. The gamma correction unit is fully user-programmable, and color saturation
Camera Interface and Test Patterns
The MT9M111 outputs processed video as a standard ITU-R BT.656 stream, an RGB stream, or as processed or unprocessed Bayer data. The ITU-R BT.656 stream contains YCbCr 4:2:2 data with optional embedded synchronization codes. This output is typically suitable for subsequent display by standard (progressive scan) video equipment, or JPEG/MPEG compression. RGB functionality provides support for LCD devices. The MT9M111 can be configured to output 16-bit RGB (RGB565), 15-bit RGB (RGB555), and two types of 12-bit RGB (RGB444). The user can configure internal
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
registers to swap odd and even bytes, chrominance channels, and luminance and chrominance components to ease interfacing to application processors. To assist in integration and system debug, a variety of test patterns are provided, from simple ramps to colorbars. * Sensor core image array readout (e.g., low-power QSXGA preview to/from full-power SXGA snapshot) * The resizer (output resolutions for preview and snapshot) * Camera interface (e.g., RGB565 for LCD preview and YCbCr for snapshots) To facilitate taking snapshots and flash snapshots, the IFP includes a camera-control sequencer that automates the process of stepping through a number of preset configurable programs. In addition to basic snapshots, there are programs for both Xenon and LED assisted snapshots. A flash-triggering controller provides an appropriate timing strobe for synchronizing the onset of flash illumination with the rolling shutter.
Contexts, Snapshots, and Flash
For a number of parameters, registers are provided for storing two "contexts": Context A and Context B. These contexts enable the user to setup the camera for a number of different modes, then switch between modes with a single register write to the Global Context Control Register (GCCR). A typical example is to use Context A for viewfinder/preview settings and Context B for snapshots. Functions supporting context switching include:
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Output Data Ordering Table 3:
MODE Default Swap CrCb SwapYC Swap CrCb, SwapYC
Data Ordering in YCbCr Mode
BYTE Cbi Cri Yi Yi Yi Yi Cbi Cri Cri Cbi Yi+1 Yi+1 Yi+1 Yi+1 Cri Cbi
Table 4:
MODE Default Flip Bayer Col Flip Bayer Row Flip Bayer Col, Flip Bayer Row
Output Data Ordering in Processed Bayer Mode
LINE First Second First Second First Second First Second BYTE Gi Bi Ri Gi Bi Gi Gi Ri Ri+1 Gi+1 Gi+1 Bi+1 Gi+1 Ri+1 Bi+1 Gi+1 Gi+2 Bi+2 Ri+2 Gi+2 Bi+2 Gi+2 Gi+2 Ri+2 Ri+3 Gi+3 Gi+3 Bi+3 Gi+3 Ri+3 Bi+3 Gi+3
Table 5:
Output Data Ordering in RGB Mode
BYTE First Second First Second First Second First Second D7 R7 G4 0 G5 R7 B7 0 G7 D6 R6 G3 R7 G4 R6 B6 0 G6 D5 R5 G2 R6 G3 R5 B5 0 G5 D4 R4 B7 R5 B7 R4 B4 0 G4 D3 R3 B6 R4 B6 G7 0 R7 B7 D2 G7 B5 R3 B5 G6 0 R6 B6 D1 G6 B4 G7 B4 G5 0 R5 B5 D0 G5 B3 G6 B3 G4 0 R4 B4
MODE (SWAP DISABLED) RGB565 RGB555 RGB444x RGBx444
Table 6:
MODE 8 + 2 bypass
Output Data Ordering in (8 + 2) Bypass Mode
BYTE First Second D7 B9 0 D6 B8 0 D5 B7 0 D4 B6 0 D3 B5 0 D2 B4 0 D1 B3 B1 D0 B2 B0
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
IFP Register List Table 7:
REGISTER #DEC (HEX) 5 (05) 6 (06) 8 (08) 16 (10) 17 (11) 18 (12) 19 (13) 20 (14) 21 (15) 27 (1B) 28 (1C) 29 (1D) 30 (1E) 37 (25) 52 (34) 53 (35) 58 (3A) 59 (3B) 60 (3C) 71 (47) 72 (48) 76 (4C) 77 (4D) 78 (4E) 80 (50) 82 (52) 83 (53) 84 (54) 85 (55) 86 (56) 87 (57) 88 (58) 104 (68) 128 (80) 129 (81) 130 (82) 131 (83) 132 (84) 133 (85) 134 (86) 135 (87) 136 (88) 137 (89)
Colorpipe Registers (Address Page 1)
REGISTER NAME Aperture Correction Operating Mode Control Output Format Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Color Saturation Control Luma Offset Luma Clip Output Format Control 2--Context A Lens Correction Parameter 1 Lens Correction Parameter 2 Reserved Test Pattern Generator Control Defect Correction Context A Defect Correction Context B Reserved Reserved Reserved Gamma Correction Parameter 1 Gamma Correction Parameter 2 Gamma Correction Parameter 3 Gamma Correction Parameter 4 Gamma Correction Parameter 5 Gamma Correction Parameter 6 Reserved Lens Correction Parameter 3 Lens Correction Parameter 4 Lens Correction Parameter 5 Lens Correction Parameter 6 Lens Correction Parameter 7 Lens Correction Parameter 8 Lens Correction Parameter 9 Lens Correction Parameter 10 Lens Correction Parameter 11 Lens Correction Parameter 12 DATA FORMAT 0000 0000 0000 dddd dddd dddd 0ddd dddd 0000 0ddd dddd dddd -- -- -- -- -- -- -- -- -- -- 0000 0000 00dd dddd dddd dddd dddd dddd dddd dddd dddd dddd 0ddd dddd dddd dddd -- -- -- 0000 0000 d000 0ddd 0000 0000 0000 0ddd 0000 0000 0000 0ddd -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) 3 (0003) 28686 (700E) 128 (0080) 61437 (EFFD) 64831 (FD3F) 16367 (3FEF) N/A N/A N/A 0 (0000) 0 (0000) N/A 512 (0200) 5 (0005) 16 (0010) 61456 (F010) 512 (0200) 1066 (042A) 1024 (0400) 24 (0018) 0 (0000) 0 (0000) 0 (0000) 10 (000A) N/A 0 (0000) 7700 (1E14) 17966 (462E) 34666 (876A) 47008 (B7A0) 57548 (E0CC) 0 (0000) 17 (0011) 7 (0007) 56588 (DD0C) 62696 (F4E8) 1276 (04FC) 57868 (E20C) 63212 (F6EC) 764 (02FC) 56588 (DD0C) 62696 (F4E8) 250 (00FA) MODULE Interp Cfg Cfg -- -- -- -- -- -- -- -- -- -- rgb2yuv Camlnt Camlnt CamInt LensCorr LensCorr -- FifoInt DfctCorr DfctCorr -- -- -- GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr -- LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 7:
REGISTER #DEC (HEX) 138 (8A) 139 (8B) 140 (8C) 141 (8D) 142 (8E) 143 (8F) 144 (90) 145 (91) 146 (92) 147 (93) 148 (94) 149 (95) 153 (99) 154 (9A) 155 (9B) 157 (9D) 158 (9E) 159 (9F) 160 (A0) 161 (A1) 162 (A2) 163 (A3) 164 (A4) 165 (A5) 166 (A6) 167 (A7) 168 (A8) 169 (A9) 170 (AA) 171 (AB) 172 (AC) 174 (AE) 175 (AF) 179 (B3) 180 (B4) 181 (B5) 182 (B6) 183 (B7) 184 (B8) 185 (B9) 186 (BA) 187 (BB) 188 (BC) 189 (BD) 190 (BE)
Colorpipe Registers (Address Page 1) (continued)
REGISTER NAME Lens Correction Parameter 13 Lens Correction Parameter 14 Lens Correction Parameter 15 Lens Correction Parameter 16 Lens Correction Parameter 17 Lens Correction Parameter 18 Lens Correction Parameter 19 Lens Correction Parameter 20 Lens Correction Parameter 21 Lens Correction Parameter 22 Lens Correction Parameter 23 Lens Correction Parameter 24 Line Counter Frame Counter Output Format Control 2--Context B Reserved Reserved Reducer Horizontal Pan--Context B Reducer Horizontal Zoom--Context B Reducer Horizontal Size--Context B Reducer Vertical Pan--Context B Reducer Vertical Zoom--Context B Reducer Vertical Size--Context B Reducer Horizontal Pan--Context A Reducer Horizontal Zoom--Context A Reducer Horizontal Size--Context A Reducer Vertical Pan--Context A Reducer Vertical Zoom--Context A Reducer Vertical Size--Context A Reducer Current Zoom Horizontal Reducer Current Zoom Vertical Reducer Zoom Step Size Reducer Zoom Control Global Clock Control Reserved Uniform Clocking Control Parameter Lens Correction Parameter 25 Lens Correction Parameter 26 Lens Correction Parameter 27 Lens Correction Parameter 28 Lens Correction Parameter 29 Lens Correction Parameter 30 Lens Correction Parameter 31 Lens Correction Parameter 32 Lens Correction Parameter 33 DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- ???? ???? ???? ???? ???? ???? ???? ???? 0ddd dddd dddd dddd -- -- 0d00 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0d00 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0d00 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0d00 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd ???? 0??? ???? ???? ???? 0??? ???? ???? dddd dddd dddd dddd 0000 00dd 0ddd dddd 0000 0000 0000 00dd -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) 34866 (8832) 56754 (DDB2) 63466 (F7EA) 2 (0002) 47646 (BA1E) 60627 (ECD3) 63473 (F7F1) 255 (00FF) 48926 (BF1E) 61142 (EED6) 63474 (F7F2) 3 (0003) N/A N/A 512 (0200) 9390 (24AE) N/A 0 (0000) 1280 (0500) 1280 (0500) 0 (0000) 1024 (0400) 1024 (0400) 0 (0000) 1280 (0500) 640 (0280) 0 (0000) 1024 (0400) 512 (0200) N/A N/A 1284 (0504) 16 (0010) 2 (0002) 32 (0020) 257 (0101) 4363 (110B) 15399 (3C27) 4362 (110A) 12834 (3222) 5643 (160B) 12836 (3224) 9228 (240C) 24124 (5E3C) 127 (007F) MODULE LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr CamInt CamInt CamInt -- -- Interp Interp Interp Interp Interp Interp Interp Interp Interp Interp Interp Interp Interp Interp Interp Interp ClockRst -- -- LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 7:
REGISTER #DEC (HEX) 191 (BF) 192 (C0) 193 (C1) 194 (C2) 195 (C3) 196 (C4) 200 (C8) 201 (C9) 202 (CA) 203 (CB) 204 (CC) 205 (CD) 206 (CE) 207 (C) 208 (D0) 220 (DC) 221 (DD) 222 (DE) 223 (DF) 224 (E0) 225 (E1) 226 (E2) 227 (E3) 240 (F0) 241 (F1)
Colorpipe Registers (Address Page 1) (continued)
REGISTER NAME Lens Correction Parameter 34 Lens Correction Parameter 35 Lens Correction Parameter 36 Lens Correction Parameter 37 Lens Correction Parameter 38 Lens Correction Parameter 39 Global Context Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Gamma Correction Parameter 7 Gamma Correction Parameter 8 Gamma Correction Parameter 9 Gamma Correction Parameter 10 Gamma Correction Parameter 11 Gamma Correction Parameter 12 Effects Mode Effects Sepia Page Map Byte-wise Address DATA FORMAT -- -- -- -- -- -- dddd dddd dddd dddd -- -- -- -- -- -- -- -- -- -- -- -- -- -- dddd dddd 0000 0ddd dddd dddd dddd dddd 0000 0000 0000 0ddd -- DEFAULT VALUE DEC (HEX) 8200 (2008) 20023 (4E37) 100 (0064) 8463 (210F) 19250 (4B32) 100 (0064) 0 (0000) N/A N/A N/A N/A N/A N/A N/A N/A 7700 (1E14) 17966 (462E) 34666 (876A) 47008 (B7A0) 57548 (E0CC) 0 (0000) 28672 (7000) 45091 (B023) 0 (0000) Reserved MODULE LensCorr LensCorr LensCorr LensCorr LensCorr LensCorr CntxCtl -- -- -- -- -- -- -- -- GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr GmaCorr Cfg --
Table 8:
REGISTER #DEC (HEX) 2 (02) 3 (03) 4 (04) 9 (09) 10 (0A) 11 (0B) 12 (0C) 13 (0D) 14 (0E) 15 (0F) 16 (10) 17 (11) 18 (12) 19 (13)
Camera Control Registers (Address Page 2)
REGISTER NAME Color Correction Parameter 1 Color Correction Parameter 2 Color Correction Parameter 3 Color Correction Parameter 4 Color Correction Parameter 5 Color Correction Parameter 6 Color Correction Parameter 7 Color Correction Parameter 8 Color Correction Parameter 9 Color Correction Parameter 10 Color Correction Parameter 11 Color Correction Parameter 12 Color Correction Parameter 13 Color Correction Parameter 14 DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) MODULE 110 (006E) 10531 (2923) 1316 (0524) 146 (0092) 22 (0016) 8 (0008) 171 (00AB) 147 (0093) 88 (0058) 77 (004D) 169 (00A9) 160 (00A0) N/A N/A ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 8:
REGISTER #DEC (HEX) 20 (14) 21 (15) 22 (16) 23 (17) 24 (18) 25 (19) 26 (1A) 27 (1B) 28 (1C) 29 (1D) 30 (1E) 31 (1F) 32 (20) 33 (21) 34 (22) 35 (23) 36 (24) 38 (26) 39 (27) 40 (28) 41 (29) 42 (2A) 43 (2B) 44 (2C) 45 (2D) 46 (2E) 47 (2F) 48 (30) 49 (31) 50 (32) 51 (33) 54 (36) 55 (37) 56 (38) 57 (39) 58 (3A) 59 (3B) 60 (3C) 61 (3D) 62 (3E) 63 (3F) 70 (46) 75 (4B) 76 (4C)
Camera Control Registers (Address Page 2) (continued)
REGISTER NAME Color Correction Parameter 15 Color Correction Parameter 16 Color Correction Parameter 17 Color Correction Parameter 18 Color Correction Parameter 19 Color Correction Parameter 20 Color Correction Parameter 21 Color Correction Parameter 22 Color Correction Parameter 23 Color Correction Parameter 24 Color Correction Parameter 25 AWB Parameter 1 AWB Parameter 2 AWB Parameter 3 AWB Parameter 4 AWB Parameter 5 AWB Parameter 6 Auto Exposure Window Horizontal Boundaries Auto Exposure Window Vertical Boundaries AWB Parameter 7 AWB Parameter 8 AWB Parameter 9 Auto Exposure Center Horizontal Window Boundaries Auto Exposure Center Vertical Window Boundaries AWB Window Boundaries Auto Exposure Target and Precision Control Auto Exposure Speed and Sensitivity Control-- Context A AWB Parameter 10 AWB Parameter 11 AWB Parameter 12 Auto Exposure Parameter 1 Auto Exposure Parameter 2 Auto Exposure Parameter 3 Auto Exposure Parameter 4 Auto Exposure Parameter 5 Auto Exposure Parameter 6 Auto Exposure Parameter 7 Auto Exposure Parameter 8 Auto Exposure Parameter 9 AWB Parameter 13 Auto Exposure Parameter 10 Auto Exposure Parameter 11 Reserved Auto Exposure Parameter 12 DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- dddd dddd dddd dddd dddd dddd dddd dddd -- -- -- dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd dddd -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) MODULE N/A 373 (0175) 22 (0016) 67 (0043) 12 (000C) 0 (0000) 21 (0015) 31 (001F) 22 (0016) 152 (0098) 76 (004C) 160 (00A0) 51220 (C814) 32896 (8080) 55648 (D960) 55648 (D960) 32512 (7F00) 32768 (8000) 32776 (8008) 61188 (EF04) 36211 (8D73) 208 (00D0) 24608 (6020) 24608 (6020) 61600 (F0A0) 3146 (0C4A) 57120 (DF20) N/A N/A N/A 5230 (146E) 30736 (7810) 768 (0300) 1088 (0440) 1676 (068C) 1676 (068C) 1676 (068C) 1676 (068C) 6105 (17D9) 7423 (1CFF) N/A 55552 (D900) 0 (0000) N/A ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr AWB AWB AWB AWB AWB AWB AutoExp AutoExp AWB AWB AWB AutoExp AutoExp AWB AutoExp AutoExp AWB AWB AWB AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AWB AutoExp AutoExp -- AutoExp
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 8:
REGISTER #DEC (HEX) 77 4D) 79 (4F) 87 (57) 88 (58) 89 (59) 90 (5A) 91 (5B) 92 (5C) 93 (5D) 94 (5E) 95 (5F) 96 (60) 97 (61) 98 (62) 99 (63) 100 (64) 101 (65) 103 (67) 104 (68) 106 (6A) 107 (6B) 108 (6C) 109 (6D) 110 (6E) 111 (6F) 112 (70) 113 (71) 114 (72) 115 (73) 116 (74) 117 (75) 118 (76) 119 (77) 120 (78) 121 (79) 122 (7A) 123 (7B) 124 (7C) 125 (7D) 130 (82) 131 (83) 132 (84) 133 (85) 134 (86) 135 (87)
Camera Control Registers (Address Page 2) (continued)
REGISTER NAME Auto Exposure Parameter 13 Reserved Auto Exposure Parameter 14 Auto Exposure Parameter 15 Auto Exposure Parameter 16 Auto Exposure Parameter 17 Flicker Control 0 Reserved Reserved Color Correction Parameter 26 Color Correction Parameter 27 Color Correction Parameter 28 Reserved Auto Exposure Digital Gains Monitor Reserved Reserved Auto Exposure Parameter 18 Auto Exposure Digital Gain Limits Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Auto Exposure Parameter 19 Auto Exposure Parameter 20 Auto Exposure Parameter 21 Auto Exposure Parameter 22 Auto Exposure Parameter 23 Auto Exposure Parameter 24 DATA FORMAT -- -- -- -- -- -- ?000 0000 0000 0ddd -- -- -- -- -- -- ???? ???? ???? ???? -- -- -- dddd dddd dddd dddd -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) MODULE N/A N/A 537 (0219) 644 (0284) 537 (0219) 644 (0284) 2 (0002) 4620 (120C) 5394 (1512) 26684 (683C) 12296 (3008) 2 (0002) 32896 (8080) N/A N/A 23036 (59FC) 0 (0000) 16400 (4010) 17 (0011) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1020 (03FC) 769 (0301) 193 (00C1) 929 (03A1) 980 (03D4) 983 (03D7) AutoExp -- AutoExp AutoExp AutoExp AutoExp FD -- -- ColorCorr ColorCorr ColorCorr -- AutoExp -- -- AutoExp AutoExp -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 8:
REGISTER #DEC (HEX) 136 (88) 137 (89) 138 (8A) 139 (8B) 140 (8C) 141 (8D) 142 (8E) 143 (8F) 144 (90) 145 (91) 146 (92) 147 (93) 148 (94) 149 (95) 150 (96) 151 (97) 152 (98) 153 (99) 156 (9C) 180 (B4) 181 (B5) 198 (C6) 199 (C7) 200 (C8) 201 (C9) 202 (CA) 203 (CB) 204 (CC) 205 (CD) 206 (CE) 207 (CF) 208 (D0) 209 (D1) 210 (D2) 211 (D3) 212 (D4) 213 (D5) 239 (EF) 240 (F0) 241 (F1) 242 (F2) 243 (F3) 244 (F4) 245 (F5)
Camera Control Registers (Address Page 2) (continued)
REGISTER NAME Auto Exposure Parameter 25 Auto Exposure Parameter 26 Auto Exposure Parameter 27 Auto Exposure Parameter 28 Auto Exposure Parameter 29 Auto Exposure Parameter 30 Auto Exposure Parameter 31 Auto Exposure Parameter 32 Auto Exposure Parameter 33 Auto Exposure Parameter 34 Auto Exposure Parameter 35 Auto Exposure Parameter 36 Auto Exposure Parameter 37 Auto Exposure Parameter 38 Reserved Reserved Reserved Reserved Auto Exposure Speed and Sensitivity Control-- Context B Reserved Reserved Reserved Reserved Global Context Control Camera Control Sequencer Parameter 1 Camera Control Sequencer Parameter 2 Camera Control Sequencer Parameter 3 Camera Control Sequencer Parameter 4 Camera Control Sequencer Parameter 5 Camera Control Sequencer Parameter 6 Camera Control Sequencer Parameter 7 Camera Control Sequencer Parameter 8 Camera Control Sequencer Parameter 9 Camera Control Sequencer Parameter 10 Context Control Parameter 1 Camera Control Sequencer Parameter 11 Camera Control Sequencer Parameter 12 AWB Parameter 14 Page Map Byte-wise Address AWB Parameter 15 Reserved Color Correction Parameter 29 Color Correction Parameter 30 DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- dddd dddd dddd dddd -- -- -- -- dddd dddd dddd dddd -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0ddd -- -- -- -- -- DEFAULT VALUE DEC (HEX) MODULE 921 (0399) 1016 (03F8) 28 (001C) 957 (03BD) 987 (03DB) 957 (03BD) 1020 (03FC) 990 (03DE) 990 (03DE) 990 (03DE) 990 (03DE) 31 (001F) 65 (0041) 867 (0363) 0 (0000) N/A 255 (00FF) 1 (0001) 57120 (DF20) 32 (0020) N/A 0 (0000) N/A 0 (0000) N/A N/A 0 (0000) 0 (0000) 8608 (21A0) 7835 (1E9B) 19018 (4A4A) 5773 (168D) 77 (004D) 0 (0000) 0 (0000) 520 (0208) 0 (0000) 8 (0008) 0 (0000) Reserved 0 (0000) 0 (0000) 110 (006E) 135 (0087) AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp AutoExp -- -- -- -- AutoExp -- -- -- -- CntxCtl CamCtl CamCtl CamCtl CamCtl CamCtl CamCtl CamCtl CamCtl CamCtl CamCtl CntxCtl CamCtl CamCtl AWB Cfg -- AWB -- ColorCorr ColorCorr
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 8:
REGISTER #DEC (HEX) 246 (F6) 247 (F7) 248 (F8) 249 (F9) 250 (FA) 251 (FB) 252 (FC) 253 (FD) 254 (FE) 255 (FF)
NOTE:
Camera Control Registers (Address Page 2) (continued)
REGISTER NAME Color Correction Parameter 31 Color Correction Parameter 32 Color Correction Parameter 33 Color Correction Parameter 34 Color Correction Parameter 35 Color Correction Parameter 36 Color Correction Parameter 37 Color Correction Parameter 38 Color Correction Parameter 39 Color Correction Parameter 40 DATA FORMAT -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) MODULE 54 (0036) 13 (000D) 171 (00AB) 136 (0088) 72 (0048) 87 (0057) 94 (005E) 122 (007A) 20543 (503F) 43136 (A880) ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr ColorCorr
Data Format Key: 0 = "Don't Care" bit. The exceptions: R0:0 and R255:0, which are hardwired R/O binary values. d = R/W bit ? = R/O bit.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
IFP Register Description Configuration
The vast majority of IFP registers associate naturally to one of the IFP modules. These modules are identified in Table 8 on page 17. Detailed register descriptions follow in Table 9. A few registers create effects across a number of module functions. These include R240 page map register (R/W); R6:1 0x106 operating mode control register (R/W); R8:1 0x108 output format control register (R/W); the R62:2 0x23E gain types and CCM threshold register--the gain threshold for CCM adjustment (R/W).
Table 9:
REGISTER# (HEX)
Colorpipe Register Description
DESCRIPTION
R5:1--0X105 - APERTURE CORRECTION Default Description Bit 3 Bits 2:0 0x0003 Aperture correction scale factor, used for sharpening. Enables automatic sharpness reduction control (see R51:2 0x233). Sharpening factor: "000"--No sharpening. "001"--25% sharpening. "010"--50% sharpening. "011"--75% sharpening. "100"--100% sharpening. "101"--125% sharpening. "110"--150% sharpening. "111"--200% sharpening. 0x700E This register specifies the operating mode of the IFP. Enables manual white balance. User can set the base matrix and color channel gains. This bit must be asserted and de-asserted with a frame in between to force new color correction settings to take effect. Enables auto exposure. Enables on-the-fly defect correction. Clips aperture corrections. Small aperture corrections (< 8) are attenuated to reduce noise amplification. Load color correction matrix 1: In manual white balance mode, triggers the loading of a new base matrix in color correction and the loading of new base sensor gain ratios. 0: Enables the matrix to be changed "offline." Enables lens-shading correction. 1: Enables lens-shading correction. Reserved. Reserved. Enables flicker detection. 1: Enables automatic flicker detection. Reserved for future expansion. Reserved. Bypasses color correction matrix. 1: Outputs "raw" color bypassing color correction. 0: Normal color processing.
R6:1--0X106 - OPERATING MODE CONTROL (R/W) Default Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 9:
Bits 3:2
Colorpipe Register Description (continued)
Auto exposure back light compensation control. "00"--Auto exposure sampling window is specified by R38:2 and R39:2 ("large window"). "01"--Auto exposure sampling window is specified by R43:2 and R44:2 ("small window"). "1X"--Auto exposure sampling window is specified by the weighted sum of the large window and the small window, with the small window weighted four times more heavily. Enables AWB. 1: Enables auto white balance. 0: Freezes white balance at current values. Reserved for future expansion. 0x0080 This register specifies the output timing and format in conjunction with R58:1 or R155:1 (depending on the context). Reserved for future expansion. Flip Bayer columns in processed Bayer output mode. 0: Column order is green, red and blue, green. 1: Column order is red, green and green, blue. Flip Bayer row in processed Bayer output mode. 0: First row contains green and red; the second row contains blue and green. 1: First row contains blue and green; the second row contains green and red. Controls the values used for the protection bits in Rec. ITU-R BT.656 codes. 0: Use zeros for the protection bits. 1: Use the correct values. Multiplexes Y (in YCbCr mode) or green (in RGB mode) channel on all channels (monochrome). 1: Forces Y/G onto all channels. Disables Cab color output channel (Cb = 128) in YCbCr mode and disables the blue color output channel (B = 0) in RGB mode. 1: Forces Cab to 128 or B to 0. Disables Y color output channel (Y = 128) in YCbCr and disables the green color output channel (G = 0) in RGB mode. 1: Forces Y to 128 or G to 0. Disables Cr color output channel (Cr = 128) in YCbCr mode and disables the red color output channel (R = 0) in RGB mode. 1: Forces Cr to 128 or R to 0. Toggles the assumptions about Bayer vertical CFA shift. 0: Row containing red comes first. 1: Row containing blue comes first. Toggles the assumptions about Bayer horizontal CFA shift. 0: Green comes first. 1: Red or blue comes first.
Bit 1
Bit 0 Default Description Bits 15:10 Bit 9
R8:1--0X108 - OUTPUT FORMAT CONTROL (R/W)
Bit 8
Bit 7
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 9:
Default Description Bit 5:3
Colorpipe Register Description (continued)
0x0005 This register specifies the color saturation control settings. Specify overall attenuation of the color saturation. "000"--Full color saturation "001"--75% of full saturation "010"--50% of full saturation "011"--37.5% of full saturation "100"--25% of full saturation "101"--150% of full saturation "110"--black and white Specify color saturation attenuation at high luminance (linearly increasing attenuation from no attenuation to monochrome at luminance of 224). "000"--No attenuation. "001"--Attenuation starts at luminance of 216. "010"--Attenuation starts at luminance of 208. "011"--Attenuation starts at luminance of 192. "100"--Attenuation starts at luminance of 160. "101"--Attenuation starts at luminance of 96. 0x0010 Offset added to the luminance prior to output. Y Offset in YCbCr mode. Offset in RGB mode. 0xF010 Clipping limits for output luminance. Highest value of output luminance. Lowest value of output luminance. 0x0200 Output format control 2A. Output processed Bayer data. Reserved Reserved Enables embedding Rec. ITU-R BT.656 synchronization codes in the output data. See R155:1 Entire image processing is bypassed and raw bayer is output directly. In YCbCr or RGB mode: 0: Normal operation, sensor core data flows through IFP. 1: Bypass IFP and output Imager data directly (full 10 bits). The image data still passes through the camera interface FIFO and the 10 bits are formatted to two output bytes through the camera interface; i.e., 8 + 2. Data rate is effectively the same as default 16-bit /per pixel modes. Auto exposure/AWB, etc. still function and control the sensor, though they are assuming some gain/correction through the colorpipe. See R155:1 Inverts output pixel clock. By default, this bit it asserted and data is launched off the falling edge of PIXCLK for capture by the receiver on the rising edge. See R155:1 Enables RGB output. 0: Output YCbCr data. 1: Output RGB format data as defined by R58:1[7:6].
R37:1--0X125 - COLOR SATURATION CONTROL (R/W)
Bit 2:0
R52:1--0X134 - LUMA OFFSET (R/W) Default Description Bits 15:8 Bits 7:0 Default Description Bits 15:8 Bits 7:0 Default Description Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
R53:1--0X135 - LUMA CLIP (R/W)
R58:1--0X13A - OUTPUT FORMAT CONTROL 2--CONTEXT A (R/W)
Bit 9 Bit 8
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 9:
Bits 7:6
Colorpipe Register Description (continued)
RGB output format: "00"--16-bit RGB565. "01"--15-bit RGB555. "10"--12-bit RGB444x. "11"--12-bit RGBx444. Bits 5:4 Test Ramp output: "00"--Off. "01"--By column. "10"--By row. "11"--By frame. Bit 3 Outputs RGB or YCbCr values are shifted 3 bits up. Use with R58:1[5:4] to test LCDs with low color depth. Bit 2 Averages two nearby chrominance bytes. See R155:1 Bit 1 In YCbCr mode swap C and Y bytes. In RGB mode, swap odd and even bytes. See R155:1 Bit 0 In YCbCr mode, swaps Cb and Cr channels. In RGB mode, swaps R and B channels. See R155:1 R72:1--0X148 - TEST PATTERN GENERATOR CONTROL (R/W) Default 0x0000 Description This register enables test pattern generation at the input of the image processor. Values greater than "0" turn on the test pattern generator. The brightness of the flat color areas depends on the value programmed (from 6-1) in this register. The value 7 produces the color bar pattern. Value 0 selects the sensor image. Bit 7 1: Forces WB digital gains to 1.0. 0: Normal operation. Bits 2:0 Test pattern selection. R76:1--0X14C - DEFECT CORRECTION--CONTEXT A (R/W) Default Description Bit 2 Bit 1 Bit 0 Default Description Bit 2 Bit 1 Bit 0 Default Description Bits 12:0 Default Description Bits 15:0 Default Description Bit 14 0x0000 Context A register with defect correction, mode enables, and calibration bits. Reserved Reserved Enables 2D defect correction. 0x0000 Context B register with defect correction, mode enables, and calibration bits. Reserved Reserved Enables 2D defect correction. N/A Use line counter to determine the number of the line currently being output. Line count. N/A Use frame counter to determine the index of the frame currently being output. Frame count. 0x0200 Output format control 2B. Output processed Bayer data.
R77:1--0X14D - DEFECT CORRECTION--CONTEXT B (R/W)
R153:1--0X199 - LINE COUNTER (R/O)
R154:1--0X19A - FRAME COUNTER (R/O)
R155:1--0X19B - OUTPUT FORMAT CONTROL 2--CONTEXT B (R/W)
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 9:
Bit 13 Bit 12 Bit 11 Bit 10
Colorpipe Register Description (continued)
Reserved. Reserved Enables embedding Rec. ITU-R BT.656 synchronization codes to the output data. See R58:1 Entire image processing is bypassed and raw bayer is output directly. In YCbCr or RGB mode: 0: Normal operation, sensor core data flows through IFP. 1: Bypass IFP and output Imager data directly (full 10 bits). The image data still passes through the camera interface FIFO and the 10 bits are formatted to two output bytes through the camera interface; i.e., 8 + 2. Data rate is effectively the same as default 16-bit /per pixel modes. Auto exposure/AWB, etc. still function and control the sensor, though they are assuming some gain/correction through the colorpipe. See R58:1 Inverts output pixel clock. By default, this bit it asserted and data is launched off the falling edge of PIXCLK for capture by the receiver on the rising edge. See R58:1 Enables RGB output. 0: Output YCbCr data. 1: Output RGB format data as defined by R155:1[7:6]. See R58:1 RGB output format: "00"--16-bit RGB565. "01"--15-bit RGB555. "10"--12-bit RGB444x. "11"--12-bit RGBx444. Test Ramp output: "00"--Off. "01"--By column. "10"--By row. "11"--By frame. Output RGB or YCbCr values are shifted 3 bits up. Use with R58:1[5:4] to test LCDs with low color depth. Averages two nearby chrominance bytes. See R58:1 In YCbCr mode swap C and Y bytes. In RGB mode, swap odd and even bytes. See R58:1 In YCbCr mode, swaps Cb and Cr channels. In RGB mode, swaps R and B channels. See R58:1 0x0000 Controls reducer horizontal pan in Context B 0: MT9V111-compatible origin at X = 0. 1: Centered origin at 640 for more convenient zoom and resize. X Pan: Unsigned offset from x = 0 (Bit 14 = 0), or two's complement from X = 640 (Bit 14 = 1). 0x0500 Controls reducer horizontal width of zoom window for field of view in Context B. X Zoom B. Must be X Size B 0x0500 Controls reducer horizontal output size in Context B. X Size B. Must be X Zoom B. 0x0000 Controls reducer vertical pan in Context B. 0: MT9V111-compatible origin at Y = 0. 1: Centered origin at Y = 512 for more convenient zoom and resize.
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Bit 9 Bit 8
Bits 7:6
Bits 5:4
Bit 3 Bit 2 Bit 1 Bit 0 Default Description Bit 14 Bits 10:0 Default Description Bits 10:0 Default Description Bits 10:0 Default Description Bit 14
R159:1--0X19F - REDUCER HORIZONTAL PAN--CONTEXT B (R/W)
R160:1--0X1A0 - REDUCER HORIZONTAL ZOOM--CONTEXT B (R/W)
R161:1--0X1A1 - REDUCER HORIZONTAL OUTPUT SIZE--CONTEXT B (R/W)
R162:1--0X1A2 - REDUCER VERTICAL PAN--CONTEXT B (R/W)
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 9:
Bits 10:0 Default Description Bits 10:0 Default Description Bits 10:0 Default Description Bit 14 Bits 10:0 Default Description Bits 10:0 Default Description Bits 10:0 Default Description Bit 14 Bits 10:0 Default Description Bits 10:0 Default Description Bits 10:0 Default Description Bits 10:0
Colorpipe Register Description (continued)
Y Pan: unsigned offset from Y = 0 (Bit 14 = 0), or two's complement from Y = 512 (Bit 14 = 1). 0x0400 Controls reducer vertical height of zoom window for field of view in Context B. Y Zoom B. Must be Y Size B. 0x0400 Controls reducer vertical output size in Context B. Y Size B. Must be Y Zoom B. 0x0000 Controls reducer horizontal pan in Context A. 0: MT9V111-compatible offset from X = 0. 1: Centered origin at 640 for more convenient zoom and resize. X Pan: Unsigned offset from X = 0 (Bit 14 = 0), or two's complement from X = 640 (Bit 14 = 1). 0x0500 Controls reducer horizontal width of zoom window for field of view in Context A. X Zoom A. Must be X Size A. 0x0280 Controls reducer horizontal output size in Context A. X Size A. Must be X Zoom A.. 0x0000 Controls reducer vertical pan in Context A. 0: MT9V111-compatible origin at Y = 0. 1: Centered origin at Y = 512 for more convenient zoom and resize. Y Pan: unsigned offset from y = 0 (Bit 14 = 0), or two's complement from Y = 512 (Bit 14 = 1). 0x0400 Controls reducer vertical height of zoom window for field of view in Context A. Y Zoom A. Must be Y Size A. 0x0200 Controls reducer vertical output size in Context A. Y SizeA. Must be Y Zoom A. N/A Current horizontal zoom. Current Zoom Window Width. After automatic zoom (R175:1), copy R171:1 to the snapshot X Zoom register R166:1 (Context A) or R160:1 (Context B) so the snapshot has the same field of view as preview. Also copy to snapshot X Size register R167:1 (Context A) or R161 (Context B) for largest snapshot. Reserved. Mask off these bits before performing the above copy operation.
R163:1--0X1A3 - REDUCER VERTICAL ZOOM--CONTEXT B (R/W)
R164:1--0X1A4 - REDUCER VERTICAL OUTPUT SIZE--CONTEXT B (R/W)
R165:1--0X1A5 - REDUCER HORIZONTAL PAN--CONTEXT A (R/W)
R166:1--0X1A6 - REDUCER HORIZONTAL ZOOM--CONTEXT A (R/W)
R167:1--0X1A7 - REDUCER HORIZONTAL OUTPUT SIZE--CONTEXT A (R/W)
R168:1--0X1A8 - REDUCER VERTICAL PAN--CONTEXT A (R/W)
R169:1--0X1A9 - REDUCER VERTICAL ZOOM--CONTEXT A (R/W)
R170:1--0X1AA - REDUCER VERTICAL OUTPUT SIZE--CONTEXT A (R/W)
R171:1--0X1AB - REDUCER CURRENT HORIZONTAL ZOOM (R/O)
Bits 15:12
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 9:
Default Description Bits 10:0
Colorpipe Register Description (continued)
N/A Current vertical zoom. Current Zoom Window Height. After automatic zoom (R175:1), copy R172:1 to the snapshot Y Zoom register R169:1 (Context A) or R163:1 (Context B) so the snapshot will have the same field of view as preview. Also copy to snapshot X Size register R170:1 (Context A) or R164 (Context B) for largest snapshot. Reserved. Mask off these bits before performing the above copy operation. 0x0504 Zoom step sizes. Should be a multiple of the aspect ratio 5:4 for SXGA or 4:3 VGA or 11:9 for CIF. Zoom step size in X. Zoom step size in Y. 0x0010 Resize interpolation and zoom control. Starts automatic "zoom out" in step sizes defined in R174:1. Starts automatic "zoom in" in step sizes defined in R174:1. Reserved. Reserved. Reserved. Auto switch to classic interpolation at full resolution. Reserved. Reserved.
R172:1--0X1AC - REDUCER CURRENT VERTICAL ZOOM (R/O)
Bits 15:12 Default Description Bits 15:8 Bits 7:0 Default Description Bit 9 Bit 8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0
R174:1--0X1AE - REDUCER ZOOM STEP SIZE (R/W)
R175:1--0X1AF - REDUCER ZOOM CONTROL (R/W)
R179:1--0X1B3 - GLOBAL CLOCK CONTROL (R/W) Default 0x0002 Description Configures assorted aspects of the clock controller. Bits 15:2 Not used. Bit 1 Tri-states pins in standby mode. Bit 0 SOC soft standby. R200:1--0X1C8 - GLOBAL CONTEXT CONTROL (R/W) Default 0x0000 Description Defines sensor and colorpipe context for current frame. Registers R200:0, R200:1, and R200:2 are shadows of each other. See description in R200:2. It is recommended that all updates to R200:n are handled by means of a write to R200:2. Bit 15:0 See R200:2[15:0]. R226:1--0X1E2 - EFFECTS MODE (R/W) Default Description Bits 15:8 Bits 2:0 0x7000 This register specifies which of several special effects to apply to each pixel passing through the pixel pipe. Solarization threshold. Specification of the effects mode. "000"--No effect (pixels pass through unchanged). "001"--Monochrome (chromas set to 0). "010"--Sepia (chromas set to the value in the Effects Sepia register). "011"--Negative (all color channels inverted). "100"--Solarize (luma conditionally inverted). "101"--Solarize2 (luma conditionally inverted, chromas inverted when luma inverted).
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 9:
Default Description Bit 15 Bits 14:8 Bit 7 Bits 6:0 Default Description Bits 2:0
Colorpipe Register Description (continued)
0xB023 This register specifies the chroma values for the sepia effect. In sepia mode, the chroma values of each pixel are set to this value. By default, this register contains a brownish color, but it can be set to an arbitrary color. Sign of Cb. Magnitude of Cb in 0.7 fixed point. Sign of Cr. Magnitude of Cr in 0.7 fixed point. 0x0000 This register specifies the register address page for the two-wire interface protocol. Page Address: "000"--Sensor address page "001"--Colorpipe address page "010"--Camera control address page N/A Special address to perform 8-bit reads and writes to the sensor. For additional information, see "Two-Wire Serial Interface Sample" on page 57 and "APPENDIX A" on page 56.
R227:1--0X1E3 - EFFECTS SEPIA (R/W)
R240:1--0X1F0 - PAGE MAP (R/W)
R241:1--0X1F1 - BYTE-WISE ADDRESS (R/W) Default Description
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 10: Camera Control Register Description
R38:2--0X226 - AUTO EXPOSURE WINDOW HORIZONTAL BOUNDARIES (R/W) Default 0x8000 Description This register specifies the left and right boundaries of the window used by the auto exposure measurement engine. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the right-most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the left-most edge of the frame. Bits 15:8 Right window boundary. Bits 7:0 Left window boundary. R39:2--0X227 - AUTO EXPOSURE WINDOW VERTICAL BOUNDARIES (R/W) Default 0x8008 Description This register specifies the top and bottom boundaries of the window used by the auto exposure measurement engine. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the bottom edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the top edge of the frame. Bits 15:8 Bottom window boundary. Bits 7:0 Top window boundary. R43:2--0X22B - AUTO EXPOSURE CENTER WINDOW HORIZONTAL BOUNDARIES (R/W) Default 0x6020 Description This register specifies the left and right boundaries of the window used by the auto exposure measurement engine in backlight compensation mode. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the right-most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the left-most edge of the frame. Bits 15:8 Right window boundary. Bits 7:0 Left window boundary. R44:2--0X22C - AUTO EXPOSURE CENTER WINDOW VERTICAL BOUNDARIES (R/W) Default 0x6020 Description This register specifies the top and bottom boundaries of the window used by the auto exposure measurement engine in backlight compensation mode. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the bottom edge of the frame, 64 (decimal) is the middle of the frame, and "0" is the top edge of the frame. Bits 15:8 Bottom window boundary. Bits 7:0 Top window boundary. R45:2--0X22D - AWB WINDOW BOUNDARIES (R/W) Default 0xF0A0 Description This register specifies the boundaries of the window used by the AWB measurement engine. Essentially, it describes the AWB measurement window in terms relative to the size of the image--horizontally, in units of 1/10ths of the width of the image; vertically, in units of 1/16 of the height of the image. So although the positioning is highly quantized, the window remains roughly in place as the resolution changes. Bits 15:12 Bottom window boundary (in units of blocks). Bits 11:8 Top window boundary (in units of blocks). Bits 7:4 Right window boundary (in units of 2 blocks). Bits 3:0 Left window boundary (in units of 2 blocks). R46:2--0X22E - AUTO EXPOSURE TARGET AND PRECISION CONTROL (R/W) Default 0x0C4A Description This register specifies the luma target of the auto exposure algorithm and the size of the window/range around the target in which no auto exposure adjustment is made. This window is centered on target, but the value programmed in the register is 1/2 of the window size. Bits 15:8 Half-size of the auto exposure stability window/range. Bits 7:0 Luma value of the auto exposure target.
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 10: Camera Control Register Description (continued)
R47:2--0X22F - AUTO EXPOSURE SPEED AND SENSITIVITY CONTROL--CONTEXT A (R/W) Default Description Bit 15 Bit 14 Bits 13:12 Bit 11 Bit 10 Bit 9 Bits 8:6 0xDF20 This register specifies the speed and sensitivity to changes of auto exposure in Context A. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Factor of reduction of the difference between current luma and target luma. In one adjustment auto exposure advances from current luma to target as follows: "000"--1/4 way going down, 1/8 going up. "001"--1/4 way in both directions. "010"--1/2 way in both directions. "011"--1/2 way going down, 1/4 going up. "100"--All the way in both directions (fast adaptation!). "101"--3/4 way in both directions. "110"--7/8 way in both directions. "111"--Reserved. Currently the same as "100"
Bit 5 Bits 4:3 Bits 2:0
Reserved Auto exposure luma is updated every N frames, where N is given by this field. Hysteresis control via time-averaged smoothing of luma data. Luma measurements for auto exposure are timeaveraged as follows: "000"--Auto exposure luma = current luma. "001"--Auto exposure luma = 1/2 current luma + 1/2 buffered value. "010"--Auto exposure luma = 1/4 current luma + 3/4 buffered value. "011"--Auto exposure luma = 1/8 current luma + 7/8 buffered value. "100"--Auto exposure luma = 1/16 current luma + 15/16 buffered value. "101"--Auto exposure luma = 1/32 current luma + 31/32 buffered value. "110"--Auto exposure luma = 1/64 current luma + 63/64 buffered value. "111"--Auto exposure luma = 1/128 current luma + 127/128 buffered value. R91:2--0X25B - FLICKER CONTROL (R/W) Default 0x0002 Description Primary flicker control register. Bit 15 (Read only) 50Hz/60Hz detected. 0: 50Hz detected. 1: 60Hz detected. Bit 2 Reserved Bit 1 When in "manual" flicker mode (R91:2[0] = 1), defines which flicker frequency to avoid. 0: Forces 50Hz detection. 1: Forces 60Hz detection. Bit 0 0: Auto flicker detection. 1: Manual mode. Default Description Bits 15:8 Bits 7:0 N/A These digital gains are applied within the IFP; they are independent of the Imager gains. Post-lens-correction digital gain (*writable if auto exposure is disabled). Pre-lens-correction digital gain (*writable if auto exposure is disabled).
R98:2--0X262 - AUTO EXPOSURE DIGITAL GAINS MONITOR (R/W*)
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MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 10: Camera Control Register Description (continued)
R103:2--0X267 - AUTO EXPOSURE DIGITAL GAIN LIMITS (R/W) Default 0x4010 Description This register specifies the upper limits of the digital gains used by the auto exposure algorithm. The values programmed to this register are 16 times the absolute gain values. The value of 16 represents the gain 1.0. Bits 15:8 Maximum limit on post-lens-correction digital gain. Bits 7:0 Maximum limit on pre-lens-correction digital gain. R156:2--0X29C - AUTO EXPOSURE SPEED AND SENSITIVITY CONTROL--CONTEXT B (R/W) Default Description Bit 15 Bit 14 Bits 13:12 Bit 11 Bit 10 Bit 9 Bits 8:6 0xDF20 This register specifies the speed and sensitivity to auto exposure changes in Context B. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Factor of reduction of the difference between current luma and target luma. In one adjustment, auto exposure advances from current luma to target as follows: "000"--1/4 way going down, 1/8 going up. "001"--1/4 way in both directions. "010"--1/2 way in both directions. "011"--1/2 way going down, 1/4 going up. "100"--All the way in both directions (fast adaptation!). "101"--3/4 way in both directions. "110"--7/8 way in both directions. "111"--Reserved. Currently the same as "100." Reserved. Auto exposure luma is updated every N frames, where N is given by this field. Hysteresis control via time-averaged smoothing of luma data. Luma measurements for auto exposure are timeaveraged as follows: "000"--Auto exposure luma = current luma. "001"--Auto exposure luma = 1/2 current luma + 1/2 buffered value. "010"--Auto exposure luma = 1/4 current luma + 3/4 buffered value. "011"--Auto exposure luma = 1/8 current luma + 7/8 buffered value. "100"--Auto exposure luma = 1/16 current luma + 15/16 buffered value. "101"--Auto exposure luma = 1/32 current luma + 31/32 buffered value. "110"--Auto exposure luma = 1/64 current luma + 63/64 buffered value. "111"--Auto exposure luma = 1/128 current luma + 127/128 buffered value.
Bit 5 Bits 4:3 Bits 2:0
R180:2--RESERVED R200:2--0X2C8 - GLOBAL CONTEXT CONTROL (R/W) Default 0x0000 Description Defines sensor and colorpipe context for current frame. Context A is typically used to define preview or viewfinder mode, while Context B is typically used for snapshots. The bits of this register directly control the respective functions, so care must be taken when writing to this register if a bad frame is to be avoided during the context switch. Bit 15 Controls assertion of sensor restart on update of global context control register. This helps ensure that the very next frame is generated with the new context (a problem with regard to exposure due to the rolling shutter). This bit is automatically cleared once the restart has occurred. 0: Do not restart sensor. 1: Restart sensor.
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 10: Camera Control Register Description (continued)
Bit 14 Bit 13 Bit 12 Reserved. Reserved. Defect correction context. See R76:1 and R77:1. 0: Context A 1: Context B Reserved. Resize/zoom context. Switch resize/zoom contexts: 0: Context A 1: Context B Output format Control 2 context. See R58:1 and R155:1. 0: Context A 1: Context B Gamma table context. 0: Context A 1: Context B Arm Xenon Flash. Blanking control. This is primarily for use by the internal sequencer when taking automated (e.g., flash) snapshots. Setting this bit stops frames from being sent over the BT656 external pixel interface. This is useful for ensuring that the desired frame during a snapshot sequence is the only frame captured by the host. 0: Do not blank frames to host. 1: Blank frames to host Reserved. Reserved. Sensor read mode context (skip mode, power mode, see R33:0 and R32:0. 0: Context A 1: Context B LED flash ON: 0: Turn off LED Flash 1: Turn on LED Flash Vertical blanking context: 0: Context A 1: Context B Horizontal blanking context: 0: Context A 1: Context B
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7 Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
R240:2--0X2F0 - PAGE MAP (R/W) Default 0x0000 Description This register specifies the register address page for the two wire interface protocol. Bits 2:0 Page address: "000"--Sensor address page. "001"--Colorpipe address page. "010"--Camera control address page. R241:2--0X2F1 - BYTE-WISE ADDRESS (R/W) Default N/A Description Special address to perform 8-bit reads and writes to the sensor. For additional information, see "Two-Wire Serial Interface Sample" on page 57 and "APPENDIX A" on page 56.
NOTE:
Registers marked "(R/W*)"are normally read-only (R/O) registers, except under special circumstances (detailed in the register description), when some or all bits of the register become read-writeable (R/W).
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Sensor Core Overview
The sensor consists of a pixel array of 1,316 x 1,048 total, an analog readout chain, 10-bit ADC with programmable gain and black offset, and timing and control.
Figure 6: Pixel Array Description
8 Black Rows (0, 0)
Figure 5: Sensor Core Block Diagram
1 Black Column
SXGA (1,280 x 1,024) + 4-pixel boundary for color correction + additional active column + additional active row = 1,289 x 1,033 active pixels 26 Black Columns
Control Register Active Pixel Sensor (APS) Array
Communication Bus to IFP Clock Sync Signals
Timing and Control
7 Black Rows (1315, 1047)
Analog Processing
ADC
10-Bit Data to IFP
Pixel Data Format Pixel Array Structure
The MT9M111 sensor core pixel array is configured as 1,316 columns by 1,048 rows (shown in Figure 6). The first 24 columns and the first 8 rows of pixels are optically black, and can be used to monitor the black level. The last 3 columns and the last 7 rows of pixels also are optically black. The black row data is used internally for the automatic black level adjustment. However, the first 8 black rows can also be read out by setting the sensor to raw data output mode (Reg0x022). There are 1,289 columns by 1,033 rows of optically-active pixels that provide a 4-pixel boundary around the SXGA (1,280 x 1,024) image to avoid boundary effects during color interpolation and correction. The additional active column and additional active row are used to enable horizontally and vertically mirrored readout to start on the same color pixel.
The MT9M111 sensor core uses an RGB Bayer color pattern, shown in Figure 7. The even-numbered rows contain green and red color pixels, and odd numbered rows contain blue and green color pixels. Even numbered columns contain green and blue color pixels; odd-numbered columns contain red and green color pixels. Because there are odd numbers of rows and columns, the color order can be preserved during mirrored readout.
Figure 7: Pixel Color Pattern Detail (Top Right Corner)
Column Readout Direction
. . .
Black Pixels Pixel (26, 8)
G
Row Readout Direction
R G
GR BG
G B
R G
G B
B
... G R G R G R G
B G B G R G BG GR BG B G B G R G B G B
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Output Data Format
The MT9M011 sensor core image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, shown in Figure 8. LINE_VALID is HIGH during the shaded region of the figure. FRAME_VALID timing is described in "APPENDIX A" on page 56.
Figure 8: Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
VALID IMAGE
HORIZONTAL BLANKING
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VERTICAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Sensor Core Register List Table 11: Sensor Registers (Address Page 0)
REGISTER# DEC (HEX) 0 (0x00) 1 (0x01) 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) 7 (0x07) 8 (0x08) 9 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 32 (0x20) 33 (0x21) 34 (0x22) 35 (0x23) 36 (0x24) 43 (0x2B) 44 (0x2C) 45 (0x2D) 46 (0x2E) 47 (0x2F) 48 (0x30) 49 (0x31) 50 (0x32) 51 (0x33) 52 (0x34) 54 (0x36) 55 (0x37) 59 (0x3B) 60 (0x3C) 61 (0x3D) 62 (0x3E) 63 (0x3F) 64 (0x40) 65 (0x41) 66 (0x42) 89 (0x59) 90 (0x5A) 91 (0x5B) REGISTER NAME Chip Version Row Start Column Start Window Height Window Width Horizontal Blanking--Context B Vertical Blanking--Context B Horizontal Blanking--Context A Vertical Blanking--Context A Shutter Width Row Speed Extra Delay Shutter Delay Reset Read Mode--Context B Read Mode--Context A Reserved Flash Control Reserved Green1 Gain Blue Gain Red Gain Green2 Gain Global Gain Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DATA FORMAT 0001 0100 0011 1010 (LSB) 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 00dd dddd dddd dddd 0ddd dddd dddd dddd 00dd dddd dddd dddd 0ddd dddd dddd dddd dddd dddd dddd dddd ddd0 000d dddd dddd 00dd dddd dddd dddd 00dd dddd dddd dddd d000 00dd 00dd dddd dd00 0ddd dddd dddd 0000 0d00 0000 dd00 -- ??dd dddd dddd dddd -- 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) 5178 (0x143A) 12 (0x000C) 30 (0x001E) 1024 (0x0400) 1280 (0x0500) 388 (0x0184) 42 (0x002A) 190 (0x00BE) 17 (0x0011) 537 (0x0219) 17 (0x0011) 0 (0x0000) 0 (0x0000) 8 (0x0008) 768 (0x0300) 1036 (0x040C) 297 (0x0129) 1544 (0x0608) 32875 (0x806B) 32 (0x0020) 32 (0x0020) 32 (0x0020) 32 (0x0020) 32 (0x0020) 1066 (0x042A) 7168 (0x1C00) 0 (0x0000) 841 (0x0349) 49177 (0xC019) 61680 (0xF0F0) 0 (0x0000) 33 (0x0021) 6688 (0x1A20) 8222 (0x201E) 8224 (0x2020) 8224 (0x2020) 8220 (0x201C) 215 (0x00D7) 1911 (0x0777) 12 (0x000C) 49167 (0xC00F) N/A
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 11: Sensor Registers (Address Page 0) (continued)
REGISTER# DEC (HEX) 92 (0x5C) 93 (0x5D) 94 (0x5E) 95 (0x5F) 96 (0x60) 97 (0x61) 98 (0x62) 99 (0x63) 100 (0x64) 101 (0x65) 112 (0x70) 113 (0x71) 114 (0x72) 115 (0x73) 116 (0x74) 117 (0x75) 118 (0x76) 119 (0x77) 120 (0x78) 121 (0x79) 122 (0x7A) 123 (0x7B) 124 (0x7C) 125 (0x7D) 126 (0x7E) 128 (0x80) 129 (0x81) 130 (0x82) 131 (0x83) 132 (0x84) 133 (0x85) 134 (0x86) 135 (0x87) 200 (0xC8) 240 (0xF0) 241 (0xF1) 245 (0xF5) 246 (0xF6) 247 (0xF7) 248 (0xF8) 249 (0xF9) 250 (0xFA) 251 (0xFB) 252 (0xFC) 253 (0xFD) REGISTER NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Context Control Page Map Byte-Wise Address Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DATA FORMAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- d000 0000 d000 dddd 0000 0000 0000 0ddd Reserved -- -- -- -- -- -- -- -- -- DEFAULT VALUE DEC (HEX) N/A N/A N/A 8989 (0x231D) 128 (0x0080) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 31498 (0x7B0A) 31498 (0x7B0A) 6414 (0x190E) 6159 (0x180F) 22322 (0x5732) 22068 (0x5634) 29493 (0x7335) 12306 (0x3012) 30978 (0x7902) 29958 (0x7506) 30474 (0x770A) 30729 (0x7809) 32006 (0x7D06) 12560 (0x3110) 126 (0x007E) 127 (0x007F) 127 (0x007F) 22282 (0x570A) 22539 (0x580B) 18188 (0x470C) 18446 (0x480E) 23298 (0x5B02) 92 (0x005C) 0 (0x0000) 0 (0x0000) Reserved 2047 (0x07FF) 2047 (0x07FF) 0 (0x0000) 0 (0x0000) 124 (0x007C) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000)
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 11: Sensor Registers (Address Page 0) (continued)
REGISTER# DEC (HEX) 255 (0xFF)
NOTE:
REGISTER NAME Chip Version
DATA FORMAT 0001 0100 0011 1010
DEFAULT VALUE DEC (HEX) 5178 (0x143A)
Data Format Key: 0 = "Don't Care" bit d = R/W bit ? = R/O bit. The exceptions: R0:0 and R255:0, which are hardwired R/O binary values.
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Sensor Core Register Descriptions Table 12: Sensor Core Register Descriptions
BIT FIELD R0:0--0X000 - CHIP VERSION (R/O) Bits 15:0 Bits 10:0 Row Start Hardwired read-only. The first row to be read out (not counting dark rows that may be read). To window the image down, set this register to the starting Y value. Setting a value less than 8 is not recommended since the dark rows should be read using Reg0x022. The first column to be read out (not counting dark columns that may be read). To window the image down, set this register to the starting X value. Setting a value below 0x18 is not recommended since readout of dark columns should be controlled by Reg0x022. Number of rows in the image to be read out (not counting dark rows or border rows that may be read). 0x143A 0xC Y YM R W R1:0--0X001 - ROW START DESCRIPTION DEFAULT SYNCED TO BAD READ/ (HEX) FRAME START FRAME WRITE
R2:0--0X002 - COLUMN START Bits 10:0 Col Start 0x1E Y YM W
R3:0--0X003 - WINDOW HEIGHT Bits 10:0 Window Height 0x400 Y YM W
R4:0--0X004 - WINDOW WIDTH Bits 10:0 Number of columns in image to be read out (not counting Window Width dark columns or border columns that may be read). R5:0--0X005 - HORIZONTAL BLANKING--CONTEXT B Bits 10:0 Horizontal Blanking B Number of blank columns in a row when Context B is chosen (bit 0, Reg0x0C8 = 1). If set smaller than the minimum value, the minimum value is used. With default settings, the minimum horizontal blanking is 202 columns in full-power readout mode and 114 columns in low-power readout mode. Number of blank rows in a frame when Context B is chosen (bit 1, Reg0x0C8 = 1). This number must be equal to or larger than the number of dark rows read out in a frame specified by Reg0x022. Number of blank columns in a row when Context A is chosen (bit 0, Reg0x0C8 = 0). The extra columns are added at the beginning of a row. If set smaller than the minimum value, the minimum value is used. With default settings, the minimum horizontal blanking is 202 columns in full-power readout mode and 114 columns in low-power readout mode. 0x184 Y YM W 0x500 Y YM W
R6:0--0X006 - VERTICAL BLANKING--CONTEXT B Bits 14:0 Vertical Blanking B 0x2A Y N W
R7:0--0X007 - HORIZONTAL BLANKING--CONTEXT A Bits 10:0 Horizontal Blanking A 0xBE Y YM W
R8:0--0X008 - VERTICAL BLANKING--CONTEXT A
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD Bits 14:0 Vertical Blanking A DESCRIPTION Number of blank rows in a frame when Context A is chosen (bit 1, Reg0x0C8 = 1). This number must be equal to or larger than the number of dark rows read out in a frame specified by Reg0x022. Integration time in number of rows. In addition to this register, the shutter delay register (Reg0x0C) and the overhead time influences the integration time for a given row time. Reserved. Invert pixel clock. When set, LINE_VALID, FRAME_VALID, and DATA_OUT are set to the falling edge of PIXCLK. When clear, they are set to the rising edge if there is no pixel clock delay. Delay PIXCLK in half-master-clock cycles. When set, the pixel clock can be delayed in increments of half-master- clock cycles compared to the synchronization of FRAME_VALID, LINE_VALID, and DATA_OUT. Pixel clock period in master clocks when full-power readout mode is used (Reg0x020/0x021, bit 10 = 0). In this case, the ADC clock has twice the clock period. If low-power readout mode is used, the pixel clock period is automatically doubled, so the ADC clock period remains the same for one programmed register value. The value "0" is not allowed, and "1" is used instead. Extra blanking inserted between frames specified in pixel clocks. Can be used to get a more exact frame rate. For integration times less than a frame, however, it might affect the integration times for parts of the image. The amount of time from the end of the sampling sequence to the beginning of the pixel reset sequence. This variable is automatically halved in low-power readout mode, so the time in use remains the same. This register has an upper value defined by the fact that the reset needs to finish prior to readout of that row to prevent changes in the row time. 0: Normal operation, updates changes to registers that affect image brightness at the next frame boundary (integration time, integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip, or row mirror. 1: Do not update any changes to these settings until this bit is returned to "0." All registers that are frame synchronized are affected by this bit setting. When set, a forced restart occurs when a bad frame is detected. This can shorten the delay when waiting for a good frame because the delay when masking out a bad frame is the integration time rather than the full frame time. DEFAULT SYNCED TO BAD READ/ (HEX) FRAME START FRAME WRITE 0x11 Y N W
R9:0--0X009 - SHUTTER WIDTH Bits 15:0 Shutter Width 0x219 Y N W
R10:0--0X00A - ROW SPEED Bits 15:13 Bit 8 Invert Pixel Clock Bits 7:4 Delay Pixel Clock Bits 3:0 Pixel Clock Speed -- 0x0 -- N -- 0 -- W
0x1
N
0
W
0x1
Y
YM
W
R11:0--0X00B - EXTRA DELAY Bits 13:0 Extra Delay 0x0 Y 0 W
R12:0--0X00C - SHUTTER DELAY Bits 10:0 Shutter Delay 0x0 Y N W
R13:0--0X00D - RESET Bit 15 Synchronize Changes 0x0 N 0 W
Bit 9 Restart Bad Frames
0x0
N
0
W
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD Bit 8 Show Bad Frames DESCRIPTION 0: Only output good frames (default) A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, or mirroring. 1: Output all frames (including bad frames) This reset signal is fed directly to the SOC part of the chip, and has no functionality in a stand-alone sensor. When set, the output pins are tri-stated. DEFAULT SYNCED TO BAD READ/ (HEX) FRAME START FRAME WRITE 0x0 N 0 W
Bit 5 Reset SOC Bit 4 Output Disable Bit 3 0: Stop sensor readout. Chip Enable 1: Normal operation. When this is returned to "1," sensor readout restarts and begins resetting the starting row in a new frame. To reduce the digital power, the master clock to the sensor can be disabled or the standby pin can be used. Bit 2 0: Normal operation (default) Analog 1: Disable analog circuitry. Standby Whenever this bit is set to "1" the chip enable bit (bit 3) should be set to "0." Bit 1 Setting this bit causes the sensor to abandon the current frame Restart and start resetting the first row. The delay before the first valid frame is read out equals the integration time. This bit always reads "0." Bit 0 Setting this bit puts the sensor in reset mode; this sets the Reset sensor to its default power-up state. Clearing this bit resumes normal operation. R32:0--0X020 - READ MODE--CONTEXT B Bit 15 0: LINE_VALID determined by bit 9. XOR Line Valid Ineffective if "Continuous" LINE_VALID is set. 1: LINE_VALID = Continuous LINE_VALID XOR FRAME_VALID. Bit 14 0: Normal LINE_VALID (default, no line valid during vertical Continuous blanking). Line Valid 1: "Continuous" LINE_VALID (continue producing LINE_VALID during vertical blanking). Bit 10 When read mode Context B is selected (bit 3, Reg0x0C8 = 1): Power Readout 0: Full-power readout mode, maximum readout speed. Mode-- 1: Low-power readout mode. Maximum readout frequency is Context B now half of the master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. Bit 9 This bit indicates whether to show the border enabled by bit 8. Show Border When bit 8 is 0, this bit has no meaning. When bit 8 is 1, this bit decides whether the border pixels should be treated as extra active pixels (1) or extra blanking pixels (0). Bit 8 When this bit is set, a 4-pixel border is output around the Over Sized active image array independent of readout mode (skip, zoom, mirror, etc.). Setting this bit therefore adds eight to the numbers of rows and columns in the frame. Bits 7:6 Reserved.
0x0 0x0 0x1
N N N
0 0 YM
W W W
0x0
N
YM
W
0x0
N
YM
W
0x0
N
YM
W
0x0
N
0
W
0x0
N
0
W
0x0
Y
YM
W
0x1
N
0
W
0x1
Y
YM
W
0x0
Y
YM
W
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD DESCRIPTION DEFAULT SYNCED TO BAD READ/ (HEX) FRAME START FRAME WRITE 0x0 Y YM W
Bit 5 0: Normal readout. Column Skip 4x 1: Readout two columns, and then skip six columns (as with rows). Bit 4 0: Normal readout. Row Skip 4x 1:Readout two rows, and then skip six rows (i.e., row 8, row 9, row 16, row 17...). Bit 3 When read mode Context B is selected (bit 3, Reg0x0C8 = 1): Column Skip 2x 0: Normal readout. --Context B 1: Readout two columns, and then skip two columns (as with rows). Bit 2 When read mode Context B is selected (bit 3, Reg0x0C8 = 1): Row Skip 2x-- 0: Normal readout. Context B 1: Readout two rows, then skip two rows (i.e., row 8, row 9, row 12, row 13...). Bit 1 Readout columns from right to left (mirrored). When set, Mirror Columns column readout starts from column (Col Start + Col Size) and continues down to (Col Start + 1). When clear, readout starts at Col Start and continues to (Col Start + Col Size - 1). This ensures that the starting color is maintained. Bit 0 Readout rows from bottom to top (upside down). When set, Mirror Rows row readout starts from row (Row Start + Row Size) and continues down to (Row Start + 1). When clear, readout starts at Row Start and continues to (Row Start + Row Size - 1). This ensures that the starting color is maintained. R33:0--0X021 - READ MODE--CONTEXT A When read mode Context A is selected (bit 3, Reg0x0C8 = 0): 0: Full-power readout mode, maximum readout speed. 1: Low-power readout mode. Maximum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. Bit 3 When read mode Context A is selected (bit 3, Reg0x0C8 = 0): Column Skip 2x 0: Normal readout. --Context A 1: Readout two columns, and then skip two columns (as with rows). Bit 2 When read mode Context A is selected (bit 3, Reg0x0C8 = 0): Row Skip 2x-- 0: Normal readout. Context A 1: Readout two rows, and then skip two rows (i.e., row 8, row 9, row 12, row 13...). R35:0--0X023 - FLASH CONTROL Bit 15 Flash Strobe Bit 14 Bit 13 Xenon Flash Read-only bit that indicates whether the FLASH_STROBE pin is enabled. Reserved. Enable Xenon flash. When set, the FLASH_STROBE output pin is pulsed HIGH for the programmed period during vertical blanking. This is achieved by keeping the integration time equal to one frame and the pulse width less than the vertical blanking time. Delay of the flash pulse measured in frames. Bit 10 Power Readout Mode-- Context A
0x0
Y
YM
W
0x0
Y
YM
W
0x0
Y
YM
W
0x0
Y
YM
W
0x0
Y
YM
W
0x1
Y
YM
W
0x1
Y
YM
W
0x1
Y
YM
W
0x0 -- 0x0
0 -- Y
0 -- N
R -- W
Bits 12:11 Frame Delay
0x0
N
N
W
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD Bit 10 End of Reset DESCRIPTION 0: In Xenon mode, the flash should be enabled after the readout of a frame. 1: In Xenon mode, the flash should be triggered after the resetting of a frame. 0: Flash should be enabled for one frame only. 1: Flash should be enabled every frame. Enables LED flash. When set, the FLASH_STROBE goes on prior to the start of a frame reset. When disabled, the FLASH_STROBE remains HIGH until readout of the current frame completes. Length of FLASH_STROBE pulse when Xenon flash is enabled. The value specifies the length in 1,024 master clock cycle increments. Initial gain = bits (6:0) x 0.03125. Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). Total gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). Total gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). Initial gain = bits (6:0) x 0.03125. DEFAULT SYNCED TO BAD READ/ (HEX) FRAME START FRAME WRITE 0x1 N N W
Bit 9 Every Frame Bit 8 LED Flash
0x1 0x0
N Y
N Y
W W
Bits 7:0 Xenon Count
0x08
N
N
W
R43:0--0X02B - GREEN1 GAIN Bits 6:0 Initial Gain Bits 8:7 Analog Gain Bits 10:9 Digital Gain Bits 10:9 Digital Gain Bits 8:7 Analog Gain Bits 6:0 Initial Gain Bits 10:9 Digital Gain Bits 8:7 Analog Gain Bits 6:0 Initial Gain Bits 10:9 Digital Gain Bits 8:7 Analog Gain Bits 6:0 Initial Gain Bits 10:0 Global Gain 0x20 0x0 0x0 Y Y Y N N N W W W
R44:0--0X02C - BLUE GAIN 0x0 0x0 0x20 Y Y Y N N N W W W
R45:0--0X02D - RED GAIN Total gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). Initial gain = bits (6:0) x 0.03125. 0x0 0x0 0x20 Y Y Y N N N W W W
R46:0--0X02E - GREEN2 GAIN Total gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain threshold (each bit gives 2x gain). Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). Initial gain = bits (6:0) x 0.03125. 0x0 0x0 0x20 Y Y Y N N N W W W
R47:0--0X02F - GLOBAL GAIN This register can be used to set all four gains at once. When read, it returns the value stored in Reg0x2B. 0x20 Y N W
R200:0--0X0C8 - CONTEXT CONTROL
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD Bit 15 Restart Bit 7 Xenon Flash Enable Bit 3 Read Mode Select Bit 2 LED Flash Enable Bit 1 Vertical Blanking Select Bit 0 Horizontal Blanking Select Bits 2:0 Page Map DESCRIPTION Setting this bit causes the sensor to abandon the current frame and start resetting the first row. Same physical register as Reg0x00D, bit 1. Enable Xenon flash. Same physical register as Reg0x023, bit 13. DEFAULT SYNCED TO BAD READ/ (HEX) FRAME START FRAME WRITE 0x0 N YM W
0x0
Y
N
W
0: Use read mode, Context A, Reg0x021. 1: Use read mode, Context B, Reg0x020. Note that bits found only in the read mode Context B register is always taken from that register. Enable LED flash. Same physical register as Reg0x023, bit 8.
0x0
Y
YM
W
0x0
Y
Y
W
0: Use vertical blanking, Context A, Reg0x008 1: Use vertical blanking, Context B, Reg0x006. 0: Use horizontal blanking, Context A, Reg0x007. 1: Use horizontal blanking, Context B, Reg0x005.
0x0
Y
YM
W
0x0
Y
YM
W
R240:0--0X0F0 - PAGE MAP Page mapping register. Must be kept at 0 to be able to write to/read from sensor. Used in the SOC to access other pages with registers. Special address to perform 8-bit (instead of 16-bit) reads and writes to the sensor. For additional information, see "TwoWire Serial Interface Sample" on page 57 and "APPENDIX A" on page 56. Hardwired value. 0x0 N 0 W
R241:0--0X0F1 - BYTE-WISE ADDRESS Bit 0 Byte-Wise Address N/A 0 0 0
R255:0--0X0FF - CHIP VERSION (R/O) Bits 15:0
NOTE:
0x143A
R
Notation used in the sensor core register description table: Sync'd to frame start 0 = Not applicable, e.g., read-only register. N = No. The register value is updated and used immediately. Y = Yes. The register value is updated at next frame start as long as the synchronize-changes bit is 0. Note also that frame start is defined as when the first dark row is read out. By default, this is 8 rows before FRAME_VALID goes HIGH. Bad frame A bad frame is a frame where all rows do not have the same integration time, or offsets to the pixel values changed during the frame. 0 = Not applicable, e.g., read-only register. N = No. Changing the register value does not produce a bad frame. Y = Yes. Changing the register value might produce a bad frame. YM = Yes, but the bad frame is masked out unless the "show bad frames" feature is enabled. Read/Write R--Read-only register/bit. W--Read/write register/bit.
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PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Sensor Read Modes and Timing
This section provides an overview of typical usage modes for the MT9M111. It focuses on two primary configurations: the first is suitable for low-power viewfinding, the second for full-resolution snapshots. It also describes mechanisms for switching between these modes. Low-Power Preview Mode QSXGA (640 x 512) images are generated at up to 30 fps. The reduced-size images are generated by skipping pixels in the sensor, i.e. decimation. The key sensor registers that define this mode are Read Mode Context A Register (R33:0) and Read Mode Context B Register (R32:0). Only certain bits in these registers are context switchable; any bits that do not have multiple contexts are always defined by their values in R32:0. Any active sets of these registers are defined by the state of R200:n[3]. On reset, R200:n[3] = 0 selecting R33:0; setups specific to preview are defined by this register. Full-Resolution Snapshot Mode SXGA (1,280 x 1,024) images are generated at up to 15 fps. This is typically selected by setting R200:n[3] = 1 selecting R32:0 (Context B) as the primary read mode register. Switching Modes Typically, switching to full-resolution or snapshot mode is achieved by writing R200:2 = 0x9F0B. This restarts the sensor and sets most contexts to Context B. Following this write, a READ from R200:1 or R200:2 results in 0x1F0B being read. Note that the most significant bit (MSB) is cleared automatically by the sensor. A READ from R200:0 results in 0x000B, as only the lower 4 bits and the restart MSB are implemented in the sensor core.
Contexts
The MT9M111 supports hardware-accelerated context switching. A number of parameters have two copies of their setup registers; this allows two "contexts" to be loaded at any given time. These are referred to as Context A and Context B. Context selection for any single parameter is determined by the Global Context Control Register (GCCR, see R200:2). There are copies of this register in each address page. A write to any one of them has the identical effect. However, a READ from address page 0 only returns the subset bits of R200 that are specific to the sensor core. The user can employ contexts for a variety of purposes; thus the generic naming convention. One typical usage model is to define Context A as "viewfinder" or "preview" mode and Context B as "snapshot" mode. The device defaults are configured with this in mind. This mechanism enables the user to have settings for viewfinder and snapshot modes loaded at the same time, and then switch between them with a single write to e.g. R200:2.
Viewfinder/Preview and Full-Resolution/Snapshot Modes
In the MT9M111, the sensor core supports two primary readout modes: low-power preview mode and full-resolution snapshot mode.
Clocks
The sensor core is a master in the system. The sensor core frame rate defines the overall image flow pipeline frame rate. Horizontal and vertical blanking are influenced by the sensor configuration, and are also a function of certain IFP functions--particularly resize. The relationship of the primary clocks are depicted in Figure 9.
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Figure 9: Primary Sensor Core Clock Relationships
CLK_IN
Div by 2
Sensor Master Clock
Sensor Core
Sensor Pixel Clock
10 bits/pixel 1 pixel/clock
Colorpipe
16 bits/pixel 1 pixel/clock
Div by N
Output FIFO
16 bits/pixel 0.5 pixel/clock
The IFP typically generates up to 16 bits per pixel, for example YCbCr or RGB565, but has only an 8-bit port through which to communicate this pixel data. There is no phase locked loop (PLL), so the primary input clock (CLKIN) must be twice the fundamental pixel rate (defined by the sensor pixel clock). To generate SXGA images at 15 fps, the sensor core requires a clock in the 24 MHZ to 27 MHz range; this is also the fundamental pixel clock rate (sensor pixel clock) for full-power operation. To achieve this pixel rate, CLKIN must be in the 48 MHz to 54 MHz range. The device defaults assume a 54 MHz clock. Minimum clock frequency is 2 MHz.
Full-Power Readout Mode The sensor is in full-resolution mode, generating 1.3 megapixels (SXGA = 1,280 x 1,024 + border) for interpolation. The SXGA image fed from the sensor to the colorpipe can be resized in the colorpipe, but the frame rate is still defined by sensor core operation. In full-power readout mode, with full field of view, the frame rate is invariant with the final image size:
Context Sensor read mode settings Sensor pixel clock
Typically Context B No skipping Full-power readout, i.e., full data rate 27 MHz for 54 MHz master clock: Maximum pixel rate of 27 megapixels/s For 54 MHz master clock, 15 fps
Primary Operating Modes
The MT9M111 supports two primary modes of operation with respect to the sensor core that affect pixel rate, frame rate and blanking:
MAX frame rate
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Low-Power Readout Mode Running under low-power readout, the sensor is in skip mode, and generates QSXGA frames (640 x 512 + border = 336,960 pixels). This full field of view QSXGA image can be resized, but only to resolutions smaller than QSXGA. The frame rate is defined by the operating mode of the sensor:
Context Sensor read mode settings Typically Context A Row skip 2x Column skip 2x Low-power readout maximum data rate is half that of full-power readout 13.5 MHz for 54 MHz master clock: Maximum pixel rate of 13.5 megapixels/s For 54 MHz master clock, 30 fps
Tuning Frame Rates Actual frame rates can be tuned by adjusting various sensor parameters. The sensor registers are in page 0, thus the ":0" after each register address:
Sensor pixel clock
Maximum frame rate
Table 13: Register Address Functions
REGISTER
R0x04:0 R0x03:0
FUNCTION
Window Width, typically 1,280 in the MT9M111 Window Height, typically 1,024 in the MT9M111
LOW-POWER READOUT MODE--CONTEXT A
R0x07:0 R0x08:0 Horizontal blanking, default is 190 (units of sensor pixel clocks) Vertical blanking, default is 17 (rows including black rows)
FULL-POWER READOUT MODE--CONTEXT B
R0x05:0 R0x06:0 Horizontal blanking, default is 388 (units of sensor pixel clocks) Vertical blanking, default is 42 (rows including black rows)
In the MT9M111, the sensor core adds four border pixels all the way around the image, taking the active image size to 1,288 x 1,032 in full-power Snapshot resolution, and 648 x 520 when skipping rows in lowpower preview resolution. This is achieved through the default settings: * Read mode Context B: R0x20:0 * Oversize and show border bits are set by default. * Oversize and show border bits are not context switchable, thus their location only in read mode Context B.
Default Blanking Calculations The MT9M111 default blanking calculations are a function of context, as follows: [REG | REG]: * Reg Low-power readout = Context A, typically used for viewfinder * Reg Full power readout = Context B, typically used for snapshots
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Table 14: Blanking Parameter Calculations
PARAMETER
PC_PERIOD Sensor Pixel Clock Period A: Active Data Time (per line): R0x04:0 + 8 (border) * PC_PERIOD Q: Horizontal Blanking: [R0x05:0 | R0x07:0] * PC_PERIOD Row Time = Q + A:
CALCULATION Full-power readout: (2/54)s = 0.0370s
Low-power readout: (4/54)s = 0.0185s
Full-power readout: A = 1288 * (2/54)s = 47.704s
Low-power readout: A = 648 * (4 / 54)s = 48.000 s
Full-power readout: Q = 388 * (2/54)s = 14.370s
Low-power readout: Q = 190 * (4/54)s = 14.074s
Full-power readout: 62.074s
Low-power readout: 62.074s
P: Frame Start / End Blanking: 6 * PC_PERIOD V: Vertical Blanking: [R0x06:0 | R0x08:0] * (Q + A) + (Q - 2 * P) F: Total Frame Time: (R0x03:0 + [R0x06:0 | R00x08:0]) * (A + Q)
NOTE:
Full-power readout: P = 6 * (2/54)s = 0.222s
Low-power readout: P = 6 * (4 / 54)s = 0.444s
Full-power readout: V = (42 * 62.074) + (14.370 - 0.444) = 2621.034 s
Low-power readout: V = (17 * 62.074) + (14.074 - 0.888) = 1068.444 s
Full-power readout: V = (1032 + 42) * 62.074s = 66667.476s 15 fps
Low-power readout: V = (520 + 17) * 62.074s = 33333.738s 30 fps
The line rate (row rate) is the same for both low-power and full-power readout modes. This ensures that when switching modes, exposure time does not change; the pre-existing shutter width remains valid.
User Blanking Calculations When calculating blanking for different clock rates, minimum values for horizontal blanking and vertical blanking must be taken into account. Table 15 shows minimum values for each register
Table 15: User Blanking Minimum Values
PARAMETER
Horizontal Blanking
REGISTER Full-power readout (Context B): R0x05:0 Low-power readout (Context A): R0x07:0 Full-power readout (Context B): R0x06:0
Low-power readout (Context A): R0x08:0
MINIMUM
202 (sensor pixel clocks) 114 (sensor pixel clocks) 5 (rows) 5 (rows)
Vertical Blanking
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Exposure and Sensor Context Switching
The MT9M111 incorporates device setup features that prevent changes in sensor context from causing a change in exposure when switching between preview/ viewfinder and full-resolution/snapshot modes. This is achieved by keeping the line rate consistent between modes. Exposure Defined by the shutter width. This is the number of lines to be reset before starting a frame read. If line rate does not change when a mode changes, exposure does not change. Switching From Context A to B Under typical/default settings, the sensor pixel rate doubles when switching from preview (Context A) to full-resolution (Context B). Additionally, the number of pixels to be read per line nearly doubles. This naturally keeps the line rates roughly equal. The difference occurs due to border pixels: for SOC operation, there are always 8 border pixels regardless of context, thus the number of pixels in each line is not quite doubled. Horizontal Blanking Defined in terms of "sensor pixel clocks." The sensor pixel clock rate doubles when switching from lowpower readout mode (preview Context A) to full-power readout mode (full-resolution Context B). To maintain the same horizontal blanking time, the value for horizontal blanking must double. This is handled by the dual, context-switchable horizontal blanking registers. Switching Modes Initiate mode switches from preview (Context A) to snapshot (Context B) during vertical blanking; switching should be accompanied by a sensor restart. Be sure R200:0[15] is written as "1" when changing contexts. Switching Frequency The user can switch between sensor contexts as frequently as necessary (without affecting exposure) with the default values for horizontal blanking and vertical blanking (R5:0-R8:0).Usefully, constant switches can occur as often as once per frame. Simple Snapshots To take a snapshot, simply switch from Context A to Context B (with restart) for a few frames, then switch back again, capturing one of the Context B frames as the snapshot. Alternative methods are supported by an internal sequencer. These additional methods are particularly useful for taking flash snapshots.
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Output Timing Figure 10: Vertical Timing
E FRAME_VALID A LINE_VALID C D B F
D[7:0]
Line 0
Line 1
LineN-3
LineN-2
LineN-1
Line 0
NO DATA
Figure 11: Horizontal Timing
PIXCLK LINE_VALID D[7:0]
10
FF
00
00
80
CB0 Y 0
CR1 Y 1
CB3 Y 3
CRn -1
Yn
FF
00
00
90
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Typical Resolutions, Modes and Timing
The parameters in Table 16 are illustrated in waveform diagram Figure 10 on page 50. Table 20 provides values for these parameters in some common resolutions and operating modes.
Table 16: Blanking Definitions
DESIGNATION (A) (B) (C) (D) (E) (F) DEFINITION FRAME_VALID (rising edge) to LINE_VALID (rising edge) delay LINE_VALID (falling edge) to FRAME_VALID (falling edge) delay LINE_VALID (HIGH/valid) time LINE_VALID (LOW/horizontal blanking) time FRAME_VALID (HIGH/valid) time FRAME_VALID (LOW/vertical blanking) time
Reset, Clocks, and Standby
Functional Operation Power-up reset is asserted/de-asserted on the RESET# pin. It is active LOW. In this reset state, all control registers have the default values. All internal clocks are turned off except for the divided-by-2 clock to the sensor core. Soft reset is asserted/de-asserted by the two-wire serial interface program. There are sensor hardmac soft resets and SOC soft resets. In soft reset mode, the two-wire serial interface and register ring bus are still running. All control registers are reset using default values. See R13:0. Hard standby is asserted/de-asserted on the STANDBY pin. It is active HIGH. In this hard standby state, all internal clocks are turned off and analog block is in standby mode to save power consumption.
(Note: following the assertion of hard standby, at least 24 master clock cycles must be delivered to complete the transition to the hard standby state.) Soft standby is asserted/de-asserted differently in the sensor page or colorpipe page. The sensor soft standby bit is in R13:0[2]. Colorpipe soft standby disables some of the SOC clocks, including the pixel clock. This bit is R179:1[0]. The colorpipe should be brought out of standby first via R179:1[0]. The colorpipe soft standby is provided to enable the user to turn off the colorpipe and the sensor independently. By default, all outputs except SDATA are disabled during hard standby. This feature can be disabled by setting R179:1[1] = 0. Independent control of the outputs is available either via the OE# pin or R13:0[4]. All outputs are implemented using bidirectional buffers, thus should not be left tri-stated. In dual camera applications, ensure that one camera is driving the bus, or that the bus is pulled to VGNDQ or VDDQ, even during standby.
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Electrical Specifications Table 17:
PARAMETER I/O digital voltage (VDDQ) Core digital voltage (VDD) Analog voltage (VAA) Pixel supply voltage (VAAPIX) Leakage current Operating Temperature
NOTE:
Electrical Characteristics and Operating Conditions
CONDITION MIN 1.7V 2.5V 2.5V 2.5V STANDBY, No clocks Measured at junction -30 TYP 2.8V 2.8V 2.8V MAX 3.6V 3.1V 3.1V 3.1V 10 +70 UNIT V V V V A C
(TA = Ambient = 25C)
VDD, VAA, and VAAPIX must all be at the same potential to avoid excessive current draw. Care must be taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together.
Table 18: I/O Parameters
PIN All Outputs PARAMETER DEFINITIONS Load capacitance Output pin slew CONDITION 2.8V, 30pF load 2.8V, 5pF load 1.8V, 30pF load 1.8V, 5pF load MIN TYP 0.72 1.25 0.34 0.51 MAX 30 UNIT pF V/ns V/ns V/ns V/ns V V mA mA mA mA V V V V 2A pF MHz MHz
VOH VOL IOH IOL IOZ VIH VIL IIN PIN CAP Freq
Output high voltage Output low voltage Output high current Output low current Tri-state output leakage current Input high voltage Input low voltage Input leakage current Pin input capacitance Master clock frequency
VDDQ = 2.8V, VOH = 2.4V VDDQ = 1.8V, VOH = 1.4V VDDQ = 2.8V, VOL = 0.4V VDDQ = 1.8V, VOL = 0.4V VDDQ = 2.8V VDDQ = 1.8V VDDQ = 2.8V VDDQ = 1.8V
16 8 15.9 10.1 1.48 0.94
26.5 15 21.3 16.2
All Inputs
1.43 0.84 -2 3.5
CLKIN
Absolute minimum SXGA @ 15 fps
2 48
54
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Power Consumption Table 19: Power Consumption at 2.8V
MODE SXGA at 15 fps QSXGA at 30 fps QSXGA at 15 fps QVGA at 30 fps SENSOR/mW 90 50 50 50 IMAGE FLOW PROC/mW 71 36 18 32 I/OS (10pF)/mW 9 4 2 1 TOTAL M/mW 170 90 70 83
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I/O Timing
By default, the MT9M111 launches pixel data, FRAME_VALID, and LINE_VALID synchronously with the falling edge of PIXCLK. The expectation is that the user captures data, FRAME_VALID, and LINE_VALID using the rising edge of PIXCLK. The timings in Figure 12 assume that the sense of PIXCLK is inverted from the default. This is achieved by setting R58:1[9] and R155:[9] = 1.
Figure 12: I/O Timing Diagram
Tclkin_min_high Tclkinr_pixclkf Tclkin_min_low Tclkin_min_period
CLKIN
Tclkinr_pixclkr Tpixclk_min_high Tpixclk_min_low
PIXCLK
Tclkinr_dout Tdout_su Tdout_ho
DATA[7:0]
Tclkinr_fvlv Tfvlv_su Tfvlv_ho
FRAME_VALID LINE_VALID
UNDEFINED
Table 20: I/O Timing Table
SLOW SIGNAL CLKIN PARAMETER CONDITIONS MIN 7.4 7.4 18.5 16.5 17.5 8.2 9.9 15.7 8.2 7.4 18.0 5.8 9.7 MAX FAST MIN 7.4 7.4 18.5 7.7 7.9 9.0 9.3 7.6 8.6 8.9 8.8 7.3 10.1 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
Tclkin_min_high Tclkin_min_low Tclkin_min_period PIXCLK Tclkinr_pixclkr Tclkinf_pixclkfl Tpixclk_min_low Tpixclk_min_high DATA[7:0] Tclkinr_dout Tdout_su Tdout_ho FRAME_VALID/LINE_VALID Tclkinr_fvlv Tfvlv_su Tfvlv_ho
16.9 17.6
7.9 8.0
50:50, 54 MHz CLKIN 50:50, 54 MHz CLKIN 50:50, 54 MHz CLKIN 50:50, 54 MHz CLKIN 50:50, 54 MHz CLKIN 50:50, 54 MHz CLKIN
18.6
8.6
21.0
9.9
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Figure 13: Spectral Response Chart (Preliminary)
Relative Spectral Response
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
350 450 550 650 750 850 950 1050
Blue Green (B) Green (R) Red
Relative Response
Wavelength (nm)
Figure 14: Optical Center Diagram
- direction + direction Die Center (0m, 0m)
-37.66m
First Clear Pixel (26, 8)
+ direction +15.63m Last Clear Pixel (1312,1040) - direction
Optical Center
NOTE:
Figure not to scale.
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APPENDIX A Serial Bus Description
Registers are written to and read from the MT9M111 through the two-wire serial interface bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK). SLCK is driven by the serial interface master. Data is transferred into and out of the MT9M111 through the serial data (SDATA) line. The SDATA line is pulled up to 2.8V off-chip by a 1.5K resistor. Either the slave or the master device can pull the SDATA line down--the two-wire serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. address. The master clocks out the register data, 8 bits at a time, and sends an acknowledge bit after each 8bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits.
Protocol
The two-wire serial interface defines several different transmission codes, as follows: * a start bit * the slave device 8-bit address. The SADDR pin is used to select between two different addresses in case of conflict with another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave address is 0xBA. * an acknowledge or a no-acknowledge bit * an 8-bit message * a stop bit.
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH.
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH.
Slave Address
The 8-bit address of a two-wire serial interface device consists of seven bits of address and 1 bit of direction. A "0" in the least significant bit (LSB) of the address indicates write mode, and a "1" indicates read mode. The write address of the sensor is 0xBA; the read address is 0xBB. This applies only when the SADDR is set HIGH.
Sequence
A typical read or write sequence begins with the master sending a start bit. After the start bit, the master sends the 8-bit slave device address. The last bit of the address determines if the request is a read or a write, where a "0" indicates a write and a "1" indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master transfers the 8bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data, 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9M111 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. The master sends the write-mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave
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Data Bit Transfer
One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock--it can only change when the serial clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver signals an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.
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Two-Wire Serial Interface Sample Write and Read Sequences (SADDR = 1) 16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 15. A start bit sent by the master starts the sequence, followed by the write address. The image sensor sends an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each 8-bit transfer, the image sensor sends an acknowledge bit. All 16 bits must be written before the register is updated. After 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit.
Figure 15: Write Timing to R0x09:0--Value 0x0284
SCLK SDATA
0xBA Address Start ACK
Reg 0x09 ACK
0000 0010 ACK
1000 0100 Stop ACK
16-Bit Read Sequence
A typical read sequence is shown in Figure 16. The master writes the register address, as in a write sequence. Then a start bit and the read address specify that a read is about to occur from the register. The master then clocks out the register data, 8 bits at a
time. The master sends an acknowledge bit after each 8-bit transfer. The register address should be incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a noacknowledge bit.
Figure 16: Read Timing from R0x09:0; Returned Value 0x0284
SCLK SDATA 0xBA Address Start ACK ACK Reg 0x09 0xBB Address Start ACK ACK NACK 0000 0010 1000 0100 Stop
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8-Bit Write Sequence
To be able to write one byte at a time to the register, a special register address is added. The 8-bit write is started by writing the upper 8 bits to the desired register, then writing the lower 8 bits to the special register address (R0xF1:0). The register is not updated until all 16 bits have been written. It is not possible to update just half of a register. Figure 17 shows a typical sequence for an 8-bit write. The second byte is written to the special register (R0xF1:0).
Figure 17: Write Timing to R0x09:0--Value 0x0284
SCLK SDATA
0xBA Address Start ACK
Reg 0x09 ACK
0000 0010 ACK
0xBA Address Start ACK
Reg 0xF1 ACK
1000 0100 Stop ACK
8-Bit Read Sequence
To read one byte at a time, the same special register address is used for the lower byte. The upper 8 bits are read from the desired register. By following this with a
read from the special register (R0xF1:0), the lower 8 bits are accessed (Figure 18). The master sets the noacknowledge bits shown.
Figure 18: Read Timing from R0x09:0; Returned Value 0x0284
Two-Wire Serial Bus Timing
The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles.
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Figure 19: Serial Host Interface: Start Condition Timing
5 SCLK SDATA SDATA 4 SCLK
Figure 21: Serial Host Interface Write
4 4
NOTE:
SDATA is driven by an off-chip transmitter.
Figure 20: Serial Host Interface: Stop Condition Timing
Figure 22: Serial Host Interface Read
NOTE: NOTE:
All timing in master clock cycle units.
SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by an off-chip pull-up resistor.
Figure 23: Acknowledge Signal Timing After an 8-Bit Write to Sensor
6 SCLK Sensor pulls down SDATA pin 3
SDATA
Figure 24: Acknowledge Signal Timing After an 8-Bit Read from Sensor
NOTE:
After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When the read sequence is complete, the master generates a no-acknowledge bit by leaving SDATA to float HIGH. On the following cycle, either a start or stop bit can be used.
09005aef8136743e pdf/09005aef8136761e zip MT9M111__SOC1310__2.fm - Rev. C 10/04 EN
59
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 25: 44-Ball iCSP Package
NOTE:
Dimensions are in millimeters MIN/MAX or typical where noted.
Data Sheet Designation: Preliminary
This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
09005aef8136743e pdf/09005aef8136761e zip MT9M111__SOC1310__2.fm - Rev. C 10/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
60
PRELIMINARY
MT9M111 SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Revision History
Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/04 * Added STANDBY to Figure 3, Typical Configuration (Connection), on page 9.
Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/04 * Updated package diagram. * Clarified low-power readout mode.
Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/04 * Initial release.
09005aef8136743e pdf/09005aef8136761e zip MT9M111__SOC1310__2.fm - Rev. C 10/04 EN
61
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.


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